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Observer gj.bucka
Observer
6,940 Views
Registered: ‎07-14-2010

5-stage MicroBlaze pipeline

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Hello all,

 

I was wondering whether anyone can explain the MicroBlaze 5-stage pipeline (C_AREA_OPTIMIZED=0) in more detail.

In the MB userguide there is only one short paragraph depicting what stages exist. There is no indication as to how the pipeline deals with hazards, i.e. is there bypassing/forwarding etc. Depending on the instruction, at what stage does stalling occur?

 

Is there any additional documentation I can read or does anyone know any more answers to this?

 

I am trying to measure clock cycles using the xps_timer but I am getting results that leave me confused, so I need to understand the underlying architecture in order to see whether the timings I receive are correct.

 

Thanks in advance for any help!

Jerome

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Xilinx Employee
Xilinx Employee
8,670 Views
Registered: ‎08-06-2007

Re: 5-stage MicroBlaze pipeline

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Hi,

 

There are some information about this in the MicroBlaze reference guide.

You can see the two different pipeline stages explained there.

 

MicroBlaze 5-stages are:

IF. Instruction fetch (Fetching the instruction)

OF: Operand fetch (All operands are resolved in this stage)

EX: Execution stage (Single clock instruction is performed here and the 1st cycle of multi-cycle instructions)

MEM: Memory stage (Load and store instructions has executed here, or 2-n cycle of multi-cycle instructions)

WB: WriteBack stage (The register file is updated)

 

All data hazards are solved for the OF stage.

 

EX stage forwarding to OF:

Integer arithmetic, logical, single bit shift, FSL input are forwarded to the OF stage

 

MEM stage forwarding to OF:

Barrel shift and integer divide are forward to the OF stage (Divide stalls many clock cycles in MEM stage until a result is calculated)

 

WB stage forwarding to OF:

All other instructions included memory load/store, fpu, multiply, ....

 

So for your assembler code: (assuming LMB or cache hits)

 

lwi r4,r0,7548   (done in one clock cycle, no stalls)

lwi r3,r0,7552  (done in one clock cycle, no stalls)

addk r3,r4,r3   (done in three clock cycles,  stalled in OF stage until "lwi r3,r0,7552" has reached WB stage)

swi r3,r0,7992 (done in one clock cycle, no stalls since addik forwarding from EX to OF)

 

I hope this give you some better understanding how the pipeline works

 

Göran

 

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6 Replies
Xilinx Employee
Xilinx Employee
6,920 Views
Registered: ‎08-01-2007

Re: 5-stage MicroBlaze pipeline

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Jerome

 

The pipeline idea for every CPU is same, you can also refer to PPC405 userguide, MB is PPC like softprocessor.

 

And, what is the informaiton you need, what the incorrect behavior you saw with timer?

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Observer gj.bucka
Observer
6,900 Views
Registered: ‎07-14-2010

Re: 5-stage MicroBlaze pipeline

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HI Joshualu,

 

thanks for the answer.

 

I have done a little more experimentation and have found that there seems to be bypassing as long as the operation is not a load word operation at which stage the result only seems to be available to next instruction after the WB stage.

 

What I wanted to know is how exactly the pipeline on the MB deals with data hazards. Like in the following assembly code:

 

lwi r4, r0, 7548
lwi r3, r0, 7552
addk r3, r4, r3
swi r3, r0, 7992

 

 

In c code that is k=i+j; If i time this I get a result of 6 clock cycles. After the different things I have tried out today I think that this is due to the lwi instruction stalling the addk instruction until the lwi instruction has written back to r3.

 

I think that this is what the pipeline will look like:

k=i+j lwi F D X M W          
lwi

F D X M W



addk


F D S S X M W
swi



F S S D X M W
      1 2 3 4 5 6    

 

Although I have to say that it seems a little odd. If there is anything that explains exactly how stalls, bypassing/forwarding is dealt with, that would be extremely helpful.

 

Thanks Jerome

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Xilinx Employee
Xilinx Employee
8,671 Views
Registered: ‎08-06-2007

Re: 5-stage MicroBlaze pipeline

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Hi,

 

There are some information about this in the MicroBlaze reference guide.

You can see the two different pipeline stages explained there.

 

MicroBlaze 5-stages are:

IF. Instruction fetch (Fetching the instruction)

OF: Operand fetch (All operands are resolved in this stage)

EX: Execution stage (Single clock instruction is performed here and the 1st cycle of multi-cycle instructions)

MEM: Memory stage (Load and store instructions has executed here, or 2-n cycle of multi-cycle instructions)

WB: WriteBack stage (The register file is updated)

 

All data hazards are solved for the OF stage.

 

EX stage forwarding to OF:

Integer arithmetic, logical, single bit shift, FSL input are forwarded to the OF stage

 

MEM stage forwarding to OF:

Barrel shift and integer divide are forward to the OF stage (Divide stalls many clock cycles in MEM stage until a result is calculated)

 

WB stage forwarding to OF:

All other instructions included memory load/store, fpu, multiply, ....

 

So for your assembler code: (assuming LMB or cache hits)

 

lwi r4,r0,7548   (done in one clock cycle, no stalls)

lwi r3,r0,7552  (done in one clock cycle, no stalls)

addk r3,r4,r3   (done in three clock cycles,  stalled in OF stage until "lwi r3,r0,7552" has reached WB stage)

swi r3,r0,7992 (done in one clock cycle, no stalls since addik forwarding from EX to OF)

 

I hope this give you some better understanding how the pipeline works

 

Göran

 

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Observer gj.bucka
Observer
6,806 Views
Registered: ‎07-14-2010

Re: 5-stage MicroBlaze pipeline

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Hello Goran,

 

thanks for that extensive answer.

 

Could you be so kind as to confirm that the color coded table in my above post does indeed conform to what you said in your post?(I=IF, D=OF,X=EX,M=MEM,W=WB)

 

I have been experimenting for the last few weeks, and what I came up with (my results) was now confimed by your answer (I think).

 

For example the same assembly code but for multiply looks like this:

 

lwi r4,r0,7548   (done in one clock cycle, no stalls)

lwi r3,r0,7552  (done in one clock cycle, no stalls)

mul r3,r4,r3   (done in three clock cycles,  stalled in OF stage until "lwi r3,r0,7552" has reached WB stage)

swi r3,r0,7992 (done in three clock cycles, stalled in OF stage until "mul r3,r4,r3" has reached WB stage)

 

Is that correct?

 

Thanks

 

Jerome

 

 

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Xilinx Employee
Xilinx Employee
6,764 Views
Registered: ‎08-06-2007

Re: 5-stage MicroBlaze pipeline

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Hi Jerome,

 

I can confirm that you color coded table above matches the assembly code.

 

The new assembly code is also correct concerning the stalling.

 

Göran

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Observer gj.bucka
Observer
6,762 Views
Registered: ‎07-14-2010

Re: 5-stage MicroBlaze pipeline

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Excellent thanks a lot Goran.

 

Above post accepted as solution!

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