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Participant mnanoop2014
Registered: ‎10-29-2018

A wrong way to use AXI interconnect?

I am in the process of synthesizing a hardware accelerator which has to access the memory inside the Zynq PS and also, Zynq PS has to be able to read and write (through AXI) to the hardware accelerator.

So I figured I use both the slave and master ports of the Zynq PS as shown in the following diagram. The problem arises when I auto-assign addresses to each of the 3 PL-PS ports and 1 PS-PL port.

Am I doing it wrong or should I just go ahead and assign addresses manually myself? Or must I use 2 AXI interconnects for PS-PL and PL-PS accesses?

Thanks in advanceScreenshot from 2019-01-09 13-13-53.png


Screenshot from 2019-01-09 13-15-16.png



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Registered: ‎02-01-2013

Re: A wrong way to use AXI interconnect?

I'm not sure what you're saving, doing the AXI connections that way. And I believe you're actually wasting resources by providing a path for the PSU AXI Master port to access the PSU AXI Slave port--which might be what's confusing the address assigner.

I would use 2 AXI interconnects: one to aggregate accesses to the PSU AXI Slave port, and the other to support accesses by the PSU AXI Master port (and any other PL AXI masters) to the AXI slaves in the PL. That will isolate the PSU AXI Master and PSU AXI Slave ports.

It's unlikely you need all of those minor AXI IP module, either. The AXI Interconnect does a good job detecting clock-domain crossings (so bye-bye, AXI Clock Converters), and combining different-width interfaces (adios, AXI Data Width Converters). Just make sure you've got the correct clocks attached to the port-clock pins of the interconnect.

-Joe G.

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