02-27-2015 10:23 AM
I am attempting to create a design with the ACP port, using the cache coherency. I have check the box in the ZYNQ7 processing system to "Tie off AxUSER" signals to always enable coherency. From reading the Zynq TRM I expect this signal should be tied high. However, after implementing the design and looking at the netlist I do not see that the AxUSER signals are even routed. Should I see AxUSER signals in the netlist? Does this mean the signals are tied high?
The Zynq TRM also mentions the AxCACHE signals. The netlist shows they are routed but the signal type is assigned GROUND. From my reading of the Zynq TRM this should be set to POWER. Is there a way to manually edit the netlist to route the AxCACHE signals to power. When I try and edit the TYPE property it says that it is read-only and refers me to UG912, which does not even list the TYPE property from what I can find.
For comparison I implemented a design the with the "Tie of AxUSER" unchecked. I see the the AxUSER signals in the netlist list as TYPE, GROUND. I assume this means it is tied to ground. The AxCACHE signals however are of TYPE, SIGNAL. I assume this means that the processor can set this signal can set this signal when preforming AXI transactions?
Neither of these cases seem correct to use the cache coherency feature of the ACP port. It seems that I need to manually edit the nets, which I am unsure how to do. Then set them either both to SIGNALs or tie them both to POWER.
Any insight into proper use of the cache coherency feature of the ACP port is appreciated.
From Zynq TRM:
ACP coherent read requests: An ACP read request is coherent when ARUSER = 1 and
ARCACHE = 1 alongside ARVALID. In this case, the SCU enforces coherency. When the data is
present in one of the Cortex-A9 processors, the data is read directly from the relevant processor, and
returned to the ACP port. When the data is not present in any of the Cortex-A9 processors, the read
request is issued on one of the SCU AXI master ports, along with all its AXI parameters, with the
exception of the locked attribute.
ACP coherent write requests: An ACP write request is coherent when AWUSER = 1 and
AWCACHE =1 alongside AWVALID. In this case, the SCU enforces coherency. When the data is
present in one of the Cortex-A9 processors, the data is first cleaned and invalidated from the
relevant CPU. When the data is not present in any of the Cortex-A9 processors, or when it has been
cleaned and invalidated, the write request is issued on one of the SCU AXI master ports, along with
all corresponding AXI parameters with the exception of the locked attribute.
02-27-2015 10:38 AM
I also took a look at AR 54683. When attempting manually assign the net of the AxUSER signals from the first case when they do not appear in the netlist. I was able to find this signal in the device view. When I right click on the signal it does not give me the "Assign Routing Mode". Other signal which are routed do have this option.
02-27-2015 10:58 AM
Using the Device View of the Implemented Design I was able to see that the AxUSER signals are connected to Physical Net GLOBAL_LOGIC1, TYPE: VCC, Route Status: Fully routed. In this same view I can see the AxCACHE signals are connected to Physical Net GLOBAL_LOGIC0, TYPE: GND, Route Status: Fully routed. Unsure why this is routed to ground.
Additionally, I mentioned when I right click on the net I am not getting the "Assign Routing Mode". This seems to be because it is selecting all of the signals attached to Physical Net GLOBAL_LOGIC0 and not the individual net SAXIACPARCACHE0.
02-15-2018 06:50 AM
did you solve your problem with AxUSER signal?
I have the same problem, as I see in "synthesized design" that AxUSER signals are connected to ground.
Actually I have connected S_AXI_ACP to AXI_DMA IP, but I see that data on DDR memory are not coherent with cache. Can it be the same problem? How did you solve it?
02-15-2018 02:37 PM
You will probably find these two threads helpful.
Make sure the Tie off AxUSER check box is set in the Zynq Processing System.
You may also need to setup the AxCACHE lines. Some info about the AxCACHE lines The simplest way is to expand the ACP port in the block diagram and wire the AxCACHE lines to a constant 0 or 1. A helpful bit of information from a post by @dylan:
Bit 0: Bufferable. Set this high.
Bit 1: Cacheable/modifiable
Bit 2: Read Allocate
Bit 3: Write Allocate
You may need experiment with the configuration a little. If you read through the threads linked above you might be able to figure out what you will want these bits set to. Unfortunately the ACP port is not well documented.