01-20-2017 06:27 AM
I´m trying to set up an embedded system which should run with 2 independent baremetal cores. I´m running Vivado 2016.2. One Baremetal core should just read Data out of the DMA and send it by LwIP. The other one reads Data via SPI and send it to the DMA. The Data which is stored in the DMA will be adapted by a VHDL program at the PL side.
My Problem is i cant run both ARM cores at the same time. I tried to realize the xapp1079 which should work like my system. But when i flash the boot.bin my fpga send nothing via uart. I followed the "Vivado instructions.txt" instructions from the xapp1079_2015_2 update. The guide says that i should verify that i use OS Version 5.19 but i have 5.5 i hope that´s okay. By building the project i had one error with the #define IRQ_PCORE_GEN_BASE.
I redefined it to #define IRQ_PCORE_GEN_BASE 0x78600000 as it was advised in:
Do i forget something to configure in the FSBL? Because i just use the normal FSBL as described in the vivado guide.
In the Information of the XAPP1079 it says:
Even tried just to run "Hello World" on both cores and just activate one UART per core in each test. When i activate UART at core0 it works well, with both program's flashed to the fpga. When i activate UART for core1 the program just stuck.
01-20-2017 04:21 PM
I may have something else that could simply your life.
We have a multi-core RTOS and offer a free version of it with limited capabilities.
As you are looking at running individual code on each core, that's the same as an application with only 2 tasks.
All you need to do is to put your code for core #0 in main() and add a function with the code for core #1 and create a task that uses this function.
You can download it from
There is a SDK demo for the 7020 (Zedboard) in the zip; I think it should work as is for the 7010.
I hope this can be helpful.