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Visitor moox
Visitor
678 Views
Registered: ‎04-10-2018

AWDT CPU Reset

Hi everyone,

 

I am trying to reset only one CPU on a Zynq7000 Device.

The CPU shall reset itself! I dont know if that is even possible?

First of all, at which address in the register map do i find the AWDT?

I assumed this is the Load Register of the AWDT 0xF8F00620?

What exactly is happening in the device when it is reseting only one CPU?

 

I started with the SCUWDT example provided with the Xilinx SDK.

It is based on interrupts so i rewrote it to reset the whole device (including the PL).

Which is working.

Then i went ahead and set the bits in the RS_AWDT_CTRL Register to only reset the CPU associated with the watchdog timer.

So what happened is that the CPU associated with the watchdog timer just stops working and is not restarting.

 

Next thing i tried is to get rid of the SCU functions and write directly to the registers of the watchdog timer.

This ended up with the same result as above. But all these SCU function calls from the example got exchanged by 2 register writes which is nice.

 

The design I am using right know is a dual core bare-metal application which boots from flash.

In the FSBL hook before Handoff function the application decides if CPU1 is required in the current configuration based upon MIO Pin states:

u32 FsblHookBeforeHandoff(void)
{
    u32 Status;
    u8 boot_mode;

    Status = XST_SUCCESS;

    /*
     * User logic to be added here.
     * Errors to be stored in the status variable and returned
     */

    // UNLOCK SLCR REGISTERS
    Xil_Out32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR + SLCR_UNLOCK_OFFSET, SLCR_UNLOCK_KEY);
    // configure MIO PIN 9 as LVCMOS33 and enable pull up
    Xil_Out32(0xF8000724, 0x00001600);
    boot_mode = ((Xil_In32(0xE000A040) & 0x00000200) >> 9);

    if(boot_mode){
        // execute normal operation mode
        // go on with basic procedure
        // normal_operation_mode();
    }else{
        // execute maintenance mode
        // start CPU1
        // write start address of cpu1
        Xil_Out32(CPU1STARTADR, 0x00200000);
        dmb(); //waits until write has finished
    }

    fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");

    return (Status);
}

 

CPU0 is running a dummy application which prints on uart plus waking up CPU1:

int main()
{
    xil_printf("CPU0:last reset due to: %08x\n\r", Xil_In32(0xF8000258));

    print("CPU0: init\n\r");

    sev();

    while(1){
        usleep(500000);
        print("CPU0 is executing Normal Operations!\n\r");
    }

    return 0;
}

CPU1 is running the AWDT source code:

void awdt_init(){
    Xil_Out32(WDT_LOAD_REG, 0xAFFEAFFE);
    /*
     * Enable Watchdog Mode
     * And Enable Watchdog
     */
    Xil_Out32(WDT_CTRL_REG, 0x00000009);
    usleep(10);
}

int main()
{
    /*
     * Unlock SLCR
     */
    Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D);

    /*
     * Enable CPU1 reset through awdt in SLCR Register
     */
    Xil_Out32(0xF800024C, 0x00000002);

    /*
     * LOCK SLCR
     */
    Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B);

    print("CPU1: init\n\r");

    awdt_init();

    while (1) {
        sleep(1);
        xil_printf("CPU1: watchdog counter reg: %08x\n\r", Xil_In32(0xF8F00624));
    }

    return 0;
}

UART-Output:

<\n>SUCCESSFUL_HANDOFF<\r>
<\n>FSBL Status = 0x1<\r>
<\n>CPU0:last reset due to: 00400000<\n><\r>
CPU0: init<\n><\r>
CPU1: init<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 9C205EF3<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 88420C5E<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 7463BCCD<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 60856D99<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 4CA71E67<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 38C8CF40<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 24EA800F<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU1: watchdog counter reg: 110C30D7<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>
CPU0 is executing Normal Operations!<\n><\r>

I attached the source files if something is missing please tell me!

Thanks for your help in advance!

 

regards,

 

Max

 

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