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Observer robin2121
Observer
492 Views
Registered: ‎07-03-2017

AXI 4 BVALID spec

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Hello !

I have a very simple question.

Assume we have in the same clock cycle :

AW_VALID = 1
AW_READY = 1

W_VALID = 1
W_READY = 1

Assume also that we have only 1 Data to send (like AXI 4-lite behavior, AWLEN = 0).

Is it AXI 4 compliant to set HIGH the B_VALID signal from the slave in the same clock cycle ?

I searched on forums and in the AXI specifications (UG 761 and the AMBA spec) but the B_VALID spec seems a little ambiguous for me :

From AMBA spec : Write transaction dependencies
"the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID. The slave must also wait for WLAST to be asserted before asserting BVALID, because the write response, BRESP, must be signaled only after the last data transfer of a write transaction"

From AMBA spec : AXI4 write response dependeny
"the slave must wait for AW_VALID, AW_READY, WVALID, and WREADY to be asserted before asserting BVALID. The slave must also wait for WLAST to be asserted before asserting BVALID because the write response, BRESP must be signaled only after the last data transfer of a write transaction"

The words "before" and "after" are ambiguous while signals are set for an entire clock cycle (theoretically of course).

Could you help me ?

PS : in attach a waveform to see the problem. 2nd case is AXI compliant. My question is about the first case.

Robin,

B_Valid_AXI4.png
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1 Solution

Accepted Solutions
Voyager
Voyager
481 Views
Registered: ‎02-01-2013

Re: AXI 4 BVALID spec

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The situation is not really that ambiguous. Note also, from the spec:

2019-02-14_13-28-04.jpg

So a master or a slave doesn't know the state of its inputs until the rising edge of a clock--i.e., when it samples those inputs.

If an output changes based on a new state of the sampled inputs, that change must necessarily occur after that same rising clock edge that sampled those inputs.

That precludes asserting BVALID before the rising clock edge that the slave uses to sample the W_READY, W_VALID and W_LAST signals--since those signals are used to determine when B_VALID can be asserted.

-Joe G.

 

 

3 Replies
Voyager
Voyager
482 Views
Registered: ‎02-01-2013

Re: AXI 4 BVALID spec

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The situation is not really that ambiguous. Note also, from the spec:

2019-02-14_13-28-04.jpg

So a master or a slave doesn't know the state of its inputs until the rising edge of a clock--i.e., when it samples those inputs.

If an output changes based on a new state of the sampled inputs, that change must necessarily occur after that same rising clock edge that sampled those inputs.

That precludes asserting BVALID before the rising clock edge that the slave uses to sample the W_READY, W_VALID and W_LAST signals--since those signals are used to determine when B_VALID can be asserted.

-Joe G.

 

 

Observer robin2121
Observer
448 Views
Registered: ‎07-03-2017

Re: AXI 4 BVALID spec

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Thanks ! I missed these lines...
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Explorer
Explorer
424 Views
Registered: ‎03-31-2016

Re: AXI 4 BVALID spec

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Also note the line below the highlighted one 

"must be no combinatorial paths between input and output signals."

Since the only way to drive BVALID high in the same clock as AWVALID and WVALID would be to do it combinationally, the definitions of before and after dont really matter in this case. 

That also means you cannot have READYs depend on their VALIDs in the same clock or RVALID on the same clock as ARVALID.

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