UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer vgl94
Observer
379 Views
Registered: ‎06-11-2018

AXI_BRAM controller writes to four addresses

Jump to solution

Hi,

I'm trying to write with MicroBlaze to a BRAM in port A and read the information back in port B through an ILA. It does write, but at four addresses at the same time.

Screenshot from 2019-10-19 16-37-34.png

 

Suppose I write at 0x00, it will also write at 0x01, 0x02 and 0x03 (but not 0x04). If I write at 0x01, it will write at 0x00, 0x01, 0x02 and 0x03 (but not at 0x04). This will also happen if I start at 0x3 or 0xff and so on. (See the code below)

The wierd thing that I'm also sniffing the port A and it doesn't change to the other addresses.

 

ila.png

Please note that my ILA sampling clock is two times that of the port A. I am using Vivado/SDK 2019.1 with KCU105.

Thank you,

#include <stdio.h>
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_io.h"

//#include "xgpio.h"
//#include "xgpio_l.h"
#include "platform.h"
#include "xil_printf.h"

#define ONE_ASCII 49
#define ENTER_ASCII 13

#define BRAM_BASE XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
#define BRAM_OFFSET 0x04
#define BRAM_TEST_DATA1 0xAAAA5522
#define BRAM_TEST_DATA2 0xAAAA5533

#define BASE 4

// don't forget to add heap = 0x800 in lscript.ld

void ClearScreen(void)
{
	xil_printf("%c\[2J", 27);
	xil_printf("%c\033[0;0H", 27);
}

u8 getChar()
{
	return XUartLite_RecvByte(XPAR_UARTLITE_0_BASEADDR);
}

void write2bram(u32 addr, u32 value)
{
	volatile u32 *LocalAddr = (volatile u32 *) (BRAM_BASE + addr);
	*LocalAddr = value;
//	Xil_Out32(BRAM_BASE + addr,value);
}

void pause_at_usr() // pause and return at UART command
{
	volatile u8 inp = 0;
	while(inp != ONE_ASCII)
	{
		inp = getChar();
	}
}

void clear_bram()
{
	for(int i = 0; i <= 0xFF;i++)
	    	write2bram(i, 0);
}

int main()
{

	int i;

    init_platform();

	ClearScreen();
    print("TEST STARTED\n\r");

    clear_bram();

        print("Shifting address");
        while(1)
        {
    		for(i = 1;i <= 10;i++)
    		{
    			pause_at_usr();
    			xil_printf("%d",i);
    			write2bram(i, BRAM_TEST_DATA2+i);
    		}
    		print("Changing to fixed address");
    		clear_bram();
    		for(i = 1;i <= 10;i++)
    		{
    			pause_at_usr();
    			xil_printf("%d",i);
    			write2bram(0, BRAM_TEST_DATA1+i);
    		}
        	print("Changing to shifting address");
        }

    print("TEST ENDED\n\r");

    cleanup_platform();
    return 0;
}

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
180 Views
Registered: ‎10-30-2017

Re: AXI_BRAM controller writes to four addresses

Jump to solution

Hi @vgl94 ,

It is expected behaviour only. the data is aligned with 32 bit (4 Byte) so you can access address 0x00, 0x04 and 0x08 etc. if you write anything at 0x00 address then data will be written to 00, 01, 02 and 03 address. the read also works as same.

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
181 Views
Registered: ‎10-30-2017

Re: AXI_BRAM controller writes to four addresses

Jump to solution

Hi @vgl94 ,

It is expected behaviour only. the data is aligned with 32 bit (4 Byte) so you can access address 0x00, 0x04 and 0x08 etc. if you write anything at 0x00 address then data will be written to 00, 01, 02 and 03 address. the read also works as same.

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

0 Kudos
Observer vgl94
Observer
144 Views
Registered: ‎06-11-2018

Re: AXI_BRAM controller writes to four addresses

Jump to solution

Hi @savula ,

Thank you for your reply.

I guess this happens inside the BRAM then, because I did not see the address change with the ILA. Do you confirm? Why is so? It seems that the FPGA is wasting precious resources...

I have also seen that this also happens with DDR.

Thank you,

0 Kudos
Xilinx Employee
Xilinx Employee
138 Views
Registered: ‎10-30-2017

Re: AXI_BRAM controller writes to four addresses

Jump to solution

Hi @vgl94 ,

This is because of the data width length of GP port in Microblaze. As the GP port data width is 32 bit you can only write to 0x00, 0x04 etc. It is not because of the BRAM. The same is applicable for DDR or any other peripheral. 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

0 Kudos