UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
587 Views
Registered: ‎04-09-2015

AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hello everyone,

 

it seems like there is a bug in the AXI CDMA IP-Core.

 

Other Posts:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-CDMA-SimpleNotDone-always-1/td-p/660591

 

Setup:

Vivado 2018.2

CDMA v4.1

 

Problem:

CDMA is not transferring multiple consecutive transfer descriptor chains without a reset between the transfer descriptor chain transfers.

 

Reproduce the problem:

1) Program the CDMA in SGMode with an external BRAM attached to the M_AXI_SG_* interface (in our case through an AXI Interconnect, also see xapp1171 as reference).

2) Program your transfer descriptor chains into the BRAM.

3) Execute the first transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

4) (optional) acknowledge interrupts.

5) Execute another transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

 

Result:

After executing the second transfer descriptor chain the CDMA gets stuck with error bits in CDMASR indicating that there has been a SGDecErr (CDMACR: 0x0001000a - CDMASR: 0x0001440a).

 

Looking at the M_AXI_SG_* interface you can see that when initiating the first transfer the correct ARADR is used.
first_transfer.png

 

When the second transfer is initiated ARADDR stays 0x0_0000_0000 which correctly results in the SGDecErr but unfortunately is not the expected result of a successfull transfer.

second_transfer.png

 

Workaround:

Reset the AXI CDMA between each transfer of a transfer descriptor chain.

 

Additional info:

We have done a lot of testing concerning how we setup the transfer descriptors and/or the CDMA before/after/between transfers, so here are just some sidenotes of what we found.

1) Reconfiguring the CDMA inbetween transfers (WITHOUT setting the reset bit) still results in a SGDecErr.

2) Reconfiguring the CDMA inbetween transfers (WITH setting the reset bit) results in correct behaviour but wastes precious clock cycles and is not what we expect in terms of issueing multiple consecutive transfers (including functionality description when reading through pg034 and xapp1171 where it says e.g. "To reuse these descriptors, update their content, initialize
the status register to zero, and update the DMA TAILDESC_PNTR register." xapp1171 p.16).

3) When using single transfer descriptors it makes no difference whether the NXTDESC_PNTR(_MSB) is set to zero or the address of the transfers descriptor itself. Both results in a SGDecErr.

4) Some goes for transfer descriptor chains which are linked in a cyclic BD chain. Stills results in SGDecErr.

5) When using the same transfer descriptor for issueing multiple transfers the transfer descriptors status register are reset before issuing the second transfers (ofc).

6) This behaviour can easily be reproduced by using a JTAG2AXI Core connected to the same AXI Interconnect as CDMA, BRAM and whatever memory component you prefer for your SA/DA.

 

Since there is no bug-report page/button/function, I post this here.

 

If there is anyone using this function successfully I am happy for any feedback.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
539 Views
Registered: ‎10-04-2016

Re: AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hi @steffen.kern,

Do you clear and set the the SGMode bit in the CDMACR register? You don't mention that in your steps.

 

Per the register definitions in PG034, this bit must be cleared to 0 and set to 1 by software to force the CDMA SG engine to use a new value written to the CURDESC_PNTR. This bit can only be changed when CDMA is idle.

 

Given this, you software should do the following:

 

1) Program the CDMA in SGMode with an external BRAM attached to the M_AXI_SG_* interface (in our case through an AXI Interconnect, also see xapp1171 as reference).

2) Program your transfer descriptor chains into the BRAM.

3) Execute the first transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

4) (optional) acknowledge interrupts.

5) Clear CDMACR.SGMode to 1'b0.

6) Set CDMACR.SGMode to 1'b1.

7) Execute another transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

 

Regards,

 

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
544 Views
Registered: ‎10-04-2016

Re: AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hi @steffen.kern,

I tried to re-create the failing scenario you describe but so far have been unable to do so. Step 5 works for me in a targeted test using the Zynq US+ MPSoC. I do not perform a soft reset between transfers.

 

I am having difficulty understanding what your system looks like to suggest other debug strategies. Are you actually recreating the design in XAPP1171 in 2018.2? Could you post your block diagram and a screen shot of the AXI CDMA configuration GUI?

 

Regards,

 

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
540 Views
Registered: ‎10-04-2016

Re: AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hi @steffen.kern,

Do you clear and set the the SGMode bit in the CDMACR register? You don't mention that in your steps.

 

Per the register definitions in PG034, this bit must be cleared to 0 and set to 1 by software to force the CDMA SG engine to use a new value written to the CURDESC_PNTR. This bit can only be changed when CDMA is idle.

 

Given this, you software should do the following:

 

1) Program the CDMA in SGMode with an external BRAM attached to the M_AXI_SG_* interface (in our case through an AXI Interconnect, also see xapp1171 as reference).

2) Program your transfer descriptor chains into the BRAM.

3) Execute the first transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

4) (optional) acknowledge interrupts.

5) Clear CDMACR.SGMode to 1'b0.

6) Set CDMACR.SGMode to 1'b1.

7) Execute another transfer descriptor chain (by programming CURDESC_PNTR than CURDESC_PNTR_MSB than TAILDESC_PNTR than TAILDESC_PNTR_MSB).

 

Regards,

 

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
Contributor
Contributor
528 Views
Registered: ‎04-09-2015

Re: AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hi @demarco

 

toggling the SGMode bit solves the problem!

Thanks for pointing that out.

 

It would be nice if the pg034 p.34 will be updated to reflect that a toggling of the SGMode bit is needed in order to initiate another transfer. There are also other information scattered throughout the documentation (e.g. how one has to set the TAILDESC_PNTR_MSB) which might benefit from more precise language, but considering that the SGMode toggle is crucial for consecutive transfers I would at least update this information on the aforementioned page.

 

Apart from that it feels wierd to be forced to toggle the SGMode in order for the engine to accept another CURDESC_PNTR. I guess there is a good reason why a fellow engineer included this. Maybe let them know, that if it's possible, it would be more straight-forward using the CDMA without the need for toggling this bit. When programming the CDMA from a CPU this also would safe additional CPU processing + data transfers between CPU and FPGA resulting in better performance.

 

Thanks again for your time to test this and pointing out the solution.

 

Cheers,

Steffen

0 Kudos
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎10-04-2016

Re: AXI CDMA SGMode multiple consecutive transfers not working

Jump to solution

Hi @steffen.kern,

I will file a change request to get the documentation updated.

 

I believe this core is in maintenance mode, so it's unlikely that a functional change would occur. Compared to our newer DMA cores, it is unusual that the bit needs to be toggled between transfers.

 

Regards,

 

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos