06-12-2014 06:19 AM
I would like to connect two Zynq-modules via AXI Chip2Chip.
Module #1should be able to access a predefined window in the DDR of Module #2:
Cpu of Module #1 -> MGPx -> Chip2Chip-Master ===> Chip2Chip-Slave -> SGPx or HPx -> DDR of Module #2
In this case I eed a translation of the address range in MGPx to DDR.
How can I realize this ?
Any other suggestions ?
06-12-2014 06:26 AM
There is a good reference design on this. Please find the link below.
This also explains the address mapping.
Hope this helps.
06-12-2014 10:32 PM
Nope. I have seen it before. This design doesnt help.
There works a vdma as Master. There are no limitation in address mapping. No translation needed.
In my application a zynq is the master.
This zynq can access the chip2chip-master through MGPx only (address 0x4000.0000 to 0x7fff.ffff or 8000.0000 to Bfff.ffff).
The DDR of the Zynq in the slave through HP0 is in range 0x2000.0000 to 0x3fff.ffff.
So I need a translation.
08-11-2015 09:28 AM
I know it's late but AXI MMU on the slave side?
08-24-2015 07:34 AM
To my best knowledge AXI MMU does not really do address translation. Could you please clarify what you mean?
06-20-2016 01:07 PM
Is there any update to this scenario. I am attempting to connect two zynq ultrascale+ devices with chip2chip and have the same questions as this original post. Also, after looking at the AXI_MMU, it would appear to be more of a filter function, not any type of translation. Is there now any method for a zynq ultrascale(+) chip2chip master to address the PS features on a zynq ultrascale(+) chip2chip slave?
02-28-2018 12:21 AM
*I try to send data from one Zynq chip to another Zynq's PS DDR3. But there is problem about the addressing and I have received VDMADecErrerror from VDMA in Master side. I gave address [2000_0000 to 3FFF_FFFF] to VDMA for AXI Chip2Chip IP, due to the Slave side Zynq PS DDR3. Because addresses of Master and Slave side of an Axi Chip2Chip bus are the exactly the same. But infact at the same time this address falls into the Master side Zynq PS DDR3. Error is this ?
*In this case, how can I send data to Slave side Zynq PS DDR3, by using VMDA in Master side through Axi Chip2Chip ?