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9,159 Views
Registered: ‎05-13-2014

AXI DMA: Data to DDR3 Memory

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Hi,

 

We are using the ZC702 Board. I'm new to the tools in Xilinx, we are switching from Altera due some problems with it, so pardon my novice understanding of Xilinx, Vivado, and all the rest....

 

We have a system where data are coming in from 8 channels at 40 MHz. We need to transfer all that data into the DDR3 via DMA. I looked around online but most of the examples are reading data from the memory via the DMA but not writing to it. Are there any good examples for this out there?

 

When we worked with one of Altera's distributors they kindly made a simply design for us to follow and we were able to get it working. It was simply a counter being written into the memory (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory), would you guys be able to provide the same.

 

Thanks,

 

Jack

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Xilinx Employee
Xilinx Employee
12,882 Views
Registered: ‎08-02-2011

Re: AXI DMA: Data to DDR3 Memory

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Yeah, sure!

 

Check the /doc/tutorial.txt file for each design for instructions on how to use them. Make sure to use the appropriate version of Vivado.

 

I'd recommend starting with the dma_ex_polled design.

www.xilinx.com

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8 Replies
Xilinx Employee
Xilinx Employee
12,883 Views
Registered: ‎08-02-2011

Re: AXI DMA: Data to DDR3 Memory

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Yeah, sure!

 

Check the /doc/tutorial.txt file for each design for instructions on how to use them. Make sure to use the appropriate version of Vivado.

 

I'd recommend starting with the dma_ex_polled design.

www.xilinx.com

View solution in original post

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9,123 Views
Registered: ‎05-13-2014

Re: AXI DMA: Data to DDR3 Memory

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Is any reason why it takes so long to compile one of these examples? For me, it takes 23 minutes for synthesis and implementation.

I thought the new Vivado is supposed to be really fast!

Jack
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9,110 Views
Registered: ‎05-13-2014

Re: AXI DMA: Data to DDR3 Memory

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Hi,

 

Just a question regarding the TREADY line coming from the S2MM.

 

How does that TREADY line behave? In the example you provided we only increment the counter when the ready line is high. But for our project, we have data coming constantly, which we assert the TVALID line when our data is there, but will the TREADY line be asserted when our data arrives?

 

Thanks,

 

Jack

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Teacher muzaffer
Teacher
9,107 Views
Registered: ‎03-31-2012

Re: AXI DMA: Data to DDR3 Memory

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If the dma block knows where the data is supposed to go, it will keep its tready valid so it will accept new data when tvalid is active too. You need to program the destination information before you expect data to arrive for this to work.
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9,053 Views
Registered: ‎05-13-2014

Re: AXI DMA: Data to DDR3 Memory

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Hi

 

It is already programmed.

 

But the TREADY line is not always on. How can we set up everything such that the TREADY is on? Since we have data coming continuously.

 

Thanks

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7,981 Views
Registered: ‎12-20-2013

Re: AXI DMA: Data to DDR3 Memory

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Hi Bwiec

 

The DMA example zip  appears tobe exactly what I want. Only problem is that i am using Vivado 2013.4, and when i run the script for the polled example it fails. Is it possible to get a later version?.

 

 (The failure message I get is:   "ip: processing_system7:5.2 is not supported for this version of the tools")

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Xilinx Employee
Xilinx Employee
7,979 Views
Registered: ‎08-02-2011

Re: AXI DMA: Data to DDR3 Memory

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Hey,

Unfortunately, the designs have not been updated at this time. You will need to run the script in 2013.4 to create the project and then migrate it forward from there.

Sorry about that!
www.xilinx.com
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7,973 Views
Registered: ‎12-20-2013

Re: AXI DMA: Data to DDR3 Memory

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Hi

 

I did run the script in 2013.4 but it literally only created the project. No design infromation was loaded.

 

Do you mean for me to  migrate it  i  will need to modifiy the script in some way?.

 

 

 

 

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