05-21-2014 02:02 PM
We are using the ZC702 Board. I'm new to the tools in Xilinx, we are switching from Altera due some problems with it, so pardon my novice understanding of Xilinx, Vivado, and all the rest....
We have a system where data are coming in from 8 channels at 40 MHz. We need to transfer all that data into the DDR3 via DMA. I looked around online but most of the examples are reading data from the memory via the DMA but not writing to it. Are there any good examples for this out there?
When we worked with one of Altera's distributors they kindly made a simply design for us to follow and we were able to get it working. It was simply a counter being written into the memory (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory), would you guys be able to provide the same.
05-21-2014 09:21 PM
05-21-2014 09:21 PM
05-22-2014 02:04 PM
05-23-2014 10:58 AM
Just a question regarding the TREADY line coming from the S2MM.
How does that TREADY line behave? In the example you provided we only increment the counter when the ready line is high. But for our project, we have data coming constantly, which we assert the TVALID line when our data is there, but will the TREADY line be asserted when our data arrives?
05-23-2014 11:35 AM
05-26-2014 03:04 PM
It is already programmed.
But the TREADY line is not always on. How can we set up everything such that the TREADY is on? Since we have data coming continuously.
11-05-2014 07:37 AM
The DMA example zip appears tobe exactly what I want. Only problem is that i am using Vivado 2013.4, and when i run the script for the polled example it fails. Is it possible to get a later version?.
(The failure message I get is: "ip: processing_system7:5.2 is not supported for this version of the tools")
11-05-2014 07:40 AM
11-05-2014 07:57 AM
I did run the script in 2013.4 but it literally only created the project. No design infromation was loaded.
Do you mean for me to migrate it i will need to modifiy the script in some way?.