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Visitor wcheng90
Visitor
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Registered: ‎05-25-2016

AXI DMA SG and ACP Slave Port

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I've been having issues interfacing the AXI DMA SG interface with the ACP port of the PS. When I have these interfaces hooked up via the Axi Interconnect, the ACP port slave returns a SLVERR. I understand that this might be related to the data limitations of the ACP port as it can only support incrementing burst reads of either 16 or 64 bytes. From what I've seen on the Chipscope ILA, when the AXI DMA SG interface requests data from the ACP port, ARSIZE is set to 4 bytes, and ARLEN = 7 (interpreted as 8 beats) for a total of 32 bytes. I'm under the impression that if I can change the amount of data the AXI DMA requests from the ACP slave to be either 16 bytes or 64 bytes, I can get the interface to work? If so, how could I reduce the burst length of the SG interface? The configuration options for the DMA core do not allow it and it seems as if adding in a AXI Width Converter wouldn't really change much because it would still request the same amount of data?

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Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎07-30-2007

Re: AXI DMA SG and ACP Slave Port

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Correct. You'll want to use the HPC ports instead. The SG is grabbing a buffer descriptor which is of fixed size.
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Xilinx Employee
Xilinx Employee
528 Views
Registered: ‎07-30-2007

Re: AXI DMA SG and ACP Slave Port

Jump to solution
Correct. You'll want to use the HPC ports instead. The SG is grabbing a buffer descriptor which is of fixed size.
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