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Participant diegosantibanez
Participant
743 Views
Registered: ‎07-25-2017

AXI DMA example failed

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Hello.

 

I'm trying to run a simple AXI DMA transfer from a Zynq UltraScale, looping it back with a FIFO.

Design:

FIFO.PNG

I'm trying to run a Xilinx example called xaxidma_example_simple_int.c.

When I run the code, I get this:

 

failed.PNG

 

Trying to debug the code, I realised that the DMA block returns an Error signal via Interrupt, so it receives the data but it's unable

to send it to the FIFO.

 

Any idea of what could I be doing wrong?

 

Thanks a lot,

Diego.

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Participant diegosantibanez
Participant
928 Views
Registered: ‎07-25-2017

Re: AXI DMA example failed

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I managed to solve the problem, but I didn't find the source tough. I was using Vivado 2017.2. I tried syntethising the exact same thing using Vivado 2018.2 and it worked. Xilinx examples are slightly different between both versions, so may be I'm missing something there.

 

Hope it helps.

Diego.

 

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Explorer
Explorer
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Registered: ‎04-19-2018

Re: AXI DMA example failed

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Same problem here on Zynq though. I was suggested to keep separated interconnects for the DMA control and data flow (as you do) so it looks like that's not the solution (for me). I will try it though.Wonder about the differnece between SmartConnect and Interconnect.

I have tried both the polling way and with interrupts. I also caught the error on the Rx interrupt. If I ignored the error then the received data doesn't match what I send.

I've been looking into this for a while but there seems not to be a clear reason and solution. 

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Participant diegosantibanez
Participant
929 Views
Registered: ‎07-25-2017

Re: AXI DMA example failed

Jump to solution

I managed to solve the problem, but I didn't find the source tough. I was using Vivado 2017.2. I tried syntethising the exact same thing using Vivado 2018.2 and it worked. Xilinx examples are slightly different between both versions, so may be I'm missing something there.

 

Hope it helps.

Diego.

 

View solution in original post

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Participant diegosantibanez
Participant
680 Views
Registered: ‎07-25-2017

Re: AXI DMA example failed

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Update: I discovered that for some reason, the module was not sending TLAST after looping back the stream DATA. That's why the DMA was sending an error flag.

 

Diego.

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Explorer
Explorer
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Registered: ‎04-19-2018

Re: AXI DMA example failed

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Same design, same software and just changing the Vivado version (and the IP versions with it as well) and you got it running?

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