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Adventurer
Adventurer
1,208 Views
Registered: ‎04-19-2018

AXI DMA example not working

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I've been trying to set up a DMA with a Zynq but for some reason is either not sending or not receiving. Attached is the design and the memory map. There is a FIFO that buffers data 16 clocks. I'm sending 32 bytes, so I expect the last 16 received match the first ones sent.

 

Software is the example for "DMA polling" in the Vivado install directory. If I run it straight away it waits forever in the highlighted while loop.

 

		Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr, MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		while ((XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) || (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))) {
				/* Wait */
		}

		Status = CheckData();

I have tried commenting out each of the XAxiDma_Busy functions, it hangs in both cases, so both the write and read seem not to end, I get this on the terminal:

dma3.png

If I skip the while loop, then, of course, it proceeds but the check function (modified to show all values) prints this:

dma4.png

 

I've been trying a lot of variations with the same frustrating results. Posts with similar problem haven't helped as well.

There are some "golden" examples by Xilinx, but they are for certain boards and certain Vivado releases, so one has to adapt them to his environment. I think DMA is a basic block and what I'm trying to do is a basic system so there should be a generic guideline instead.

dma1.png
dma2.png
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1 Solution

Accepted Solutions
Adventurer
Adventurer
1,289 Views
Registered: ‎04-19-2018

Re: AXI DMA example not working

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that's finally fixed and running. nothing wrong with the hardware or software. All I needed was an AxiStream Interconnect between the DMA and the Stream FIFO. Design below:

workingdma.png

 

 

And memory map:

 

workingmemmap.png

 

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6 Replies
Observer kruucian
Observer
1,151 Views
Registered: ‎05-18-2018

Re: AXI DMA example not working

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Hello, satguy

 

Stream FIFO seems does not attached properly

check the hardware architecture again

 

If FIFO attached properly, It will appear under AXI DMA on address editor.

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Adventurer
Adventurer
1,147 Views
Registered: ‎04-19-2018

Re: AXI DMA example not working

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@kruucian, AXI-stream is not memory mapped, there are no addresses for it, am I right or deeply confused?

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Observer kruucian
Observer
1,122 Views
Registered: ‎05-18-2018

Re: AXI DMA example not working

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sorry, satguy

 

I've confused with CDMA, you're right.

 

but there are three things of concern.

 

1. The problem that stalled in standalone is that the FIFO is inaccessible.

 

2. The odd value read from petalinux is likely to be that the data in the cache has been read.

 

3. In Zynq Ultrascale +, FIFO is registered as PS slave.

 

If you do not have to use a stream FIFO, CDMA is easier to use.

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Adventurer
Adventurer
1,117 Views
Registered: ‎04-19-2018

Re: AXI DMA example not working

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I'm not using petalinux but bare.

Is not Ultrascale+, just Zynq, but I suppose it applies.

CDMA moves from MM to MM, I need to stream, I can't use that. 

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Adventurer
Adventurer
1,290 Views
Registered: ‎04-19-2018

Re: AXI DMA example not working

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that's finally fixed and running. nothing wrong with the hardware or software. All I needed was an AxiStream Interconnect between the DMA and the Stream FIFO. Design below:

workingdma.png

 

 

And memory map:

 

workingmemmap.png

 

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Visitor airbu
Visitor
675 Views
Registered: ‎10-04-2018

Re: AXI DMA example not working

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hi @satguy,

I would like to understand why adding an axi stream interconnect and changing the address map of the axi_dma_0 from 4k to 16k solved the problem ?

As far as i know we don't need an axi stream interconnect ?

Thanks 

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