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Visitor m.valeyrie
Visitor
811 Views
Registered: ‎01-03-2018

AXI DMA problem

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Hi everybody,

 

I'm newbie with AXI DMA transfers  and I detected something weird.

 

I try to write 64-bit datas from ADC to DDR memory on Zedboard. Datas first go through an AXI Stream Fifo and I connected directly this fifo to DMA. I want to use simple polled transfer so I just modify the xilinx example code a little to get continuous DMA 64-bit transfers and to see data signals with chipscopes.

 

I give you in attachement a little hardware overview the DMA settings and a screenshot from chipscopes.

The two first signals represent the same net (between fifo and DMA) and the samples are correct. The last one is the DMA output and samples are incorrect. What's wrong ?

 

I'm at your disposal for any information you may need and I thank you in advance.

capt_DMAconnexion.png
capt_dma_settings.png
DMA_in_out_3.PNG
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1 Solution

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Visitor m.valeyrie
Visitor
843 Views
Registered: ‎01-03-2018

Re: AXI DMA problem

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The problem came from tlast signal.

My custom IP did not provide it but DMA NEED it. So I implemented an AXI_subset_stream IP (placed between custom IP and FIFO stream) to generate tlast and to correctly interface the FIFO and then the DMA.

It works pretty well now.

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8 Replies
Explorer
Explorer
786 Views
Registered: ‎01-13-2018

Re: AXI DMA problem

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I guess your ADC is sending data and you have first stored the data in FIFO through S_AXIS FIFO.  The output of M_AXIS of FIFO is then connected to S_AXIS_S2MM of AXI DMA which you want to configure in simple register mode, is that right ? and the output of AXI DMA i.e. M_AXI_S2MM is then connected to S_AXI_HP0 of Processing System through an interconnect. 

 

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Visitor m.valeyrie
Visitor
783 Views
Registered: ‎01-03-2018

Re: AXI DMA problem

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Exactly!
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Explorer
Explorer
769 Views
Registered: ‎01-13-2018

Re: AXI DMA problem

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Hello, are you using this example "xaxidma_example_simple_poll.c" available in the installation directory ? 

 

D:\Programs\Xilinx_Vivado\SDK\2017.3\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_4\examples

 

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Visitor m.valeyrie
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764 Views
Registered: ‎01-03-2018

Re: AXI DMA problem

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Yes, but I changed some things. I excluded all about MM2S transfer, checkdata function, and "for" statement. I put a while(1) before DMA transfer function. So the program runs to infinite.
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Explorer
Explorer
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Registered: ‎01-13-2018

Re: AXI DMA problem

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I have send you a message. I have a question how you feed data in FIFO. I see that it has S_AXIS. Have you made and tested a custom Master AXI Block for this which receives ADC data through non-AXI interface ? or how do you connect S_AXIS of FIFO to ADC. 

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Visitor m.valeyrie
Visitor
747 Views
Registered: ‎01-03-2018

Re: AXI DMA problem

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I forgot to explain this part. I created a custom Axi stream ip. I replaced all vhdl by just a simple condition on tready signal, tvalid, and data. Then data in are connected to data out only if tready from fifo is high.
That part seems to work properly.
I am not using tlast signal or any others from axis interface for this ip and the fifo. Then I get a warning saying no tlast is connected to DMA interface port. Is that a problem?
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Explorer
Explorer
734 Views
Registered: ‎01-13-2018

Re: AXI DMA problem

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I am also working on similar problem but instead of ADC data at the moment I have a Sample Generator with M_AXIS interface which is directly connected to S_AXIS_S2MM of AXI DMA and then M_AXI_S2MM of AXI DMA is connected to the Processing System. I have made connections in Vivado and also have simulated the Sample Generator which looks OK and can drive S_AXIS_S2MM signals of AXI DMA. 

  

I also have created a custom AXI stream IP which is my Sample Generator. There in the custom code I put a condition on tready (watching if AXI DMA is ready) if it is high then Sample Generator send data (32 bit counter) with tvalid signal but I am also using "tlast" signal generated from Sample Generated as an output because I am sending data in Frames. Each Frame consist of size eight. Upon the completion of eight counter values, the signal tlast get high and if tready is still high it continue with increment data for next Frame. During the increments the signal tlast remain down at 0. I can also share simulation results as attachment if you are interested to see. I am not sure if it is OK to leave tlast signal un-connected. 

 

I have simulated customized version of AXI stream IP (which generate counter data) in Modelsim but I am not sure if waveform inspection is enough for custom AXI stream IP as a verification. Do we need to simulate it with the Xilinx AXI Bus Functional Model ?  

 

In AXI DMA there is also a signal "s_axis_s2mm_tkeep[3:0]" how did you connect it ?. I have connected this to all 1's. 

 

 

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Visitor m.valeyrie
Visitor
844 Views
Registered: ‎01-03-2018

Re: AXI DMA problem

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The problem came from tlast signal.

My custom IP did not provide it but DMA NEED it. So I implemented an AXI_subset_stream IP (placed between custom IP and FIFO stream) to generate tlast and to correctly interface the FIFO and then the DMA.

It works pretty well now.

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