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Adventurer
Adventurer
6,260 Views
Registered: ‎10-24-2007

AXI DMA with custom AXI streaming IP in Zynq

Hi,

 

I am testing a custom IP(default one created by CIP - simple 8 word accumulator) based on AXI STREAMING interface, where the IP is connected to a AXI DMA that transfers data from the OCM and back. Though the data returned is correct, the status register of the DMA-S2MM shows a assertion on the following pins. Halted, DMAIntErr, IOC_Irq and Err_Irq. Tlast is driven zero constantly by the generated IP. DMA halts because it doesn't detect the TLast? Is there any other configuration issue?

 

The MHS file sections are as follows and the c file is attached.


BEGIN test_axis
PARAMETER INSTANCE = test_axis_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE M_AXIS = test_axis_0_M_AXIS
BUS_INTERFACE S_AXIS = axi_dma_0_M_AXIS_MM2S
PORT ACLK = processing_system7_0_FCLK_CLK0
PORT ARESETN = processing_system7_0_FCLK_RESET0_N
END

 

BEGIN axi_dma
PARAMETER INSTANCE = axi_dma_0
PARAMETER HW_VER = 6.03.a
PARAMETER C_INCLUDE_SG = 0
PARAMETER C_GENERIC = 1
PARAMETER C_BASEADDR = 0x40400000
PARAMETER C_HIGHADDR = 0x4040ffff
BUS_INTERFACE S_AXI_LITE = axi_lite
BUS_INTERFACE M_AXI_MM2S = axi_hp
BUS_INTERFACE M_AXI_S2MM = axi_hp
BUS_INTERFACE S_AXIS_S2MM = test_axis_0_M_AXIS
BUS_INTERFACE M_AXIS_MM2S = axi_dma_0_M_AXIS_MM2S
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_s2mm_aclk = processing_system7_0_FCLK_CLK0
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
PORT mm2s_introut = axi_dma_0_mm2s_introut
PORT s2mm_introut = axi_dma_0_s2mm_introut
PORT axi_resetn = processing_system7_0_FCLK_RESET0_N
END

 

BEGIN axi_interconnect
PARAMETER INSTANCE = axi_hp
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi_lite
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

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5 Replies
Adventurer
Adventurer
6,248 Views
Registered: ‎10-24-2007

Re: AXI DMA with custom AXI streaming IP in Zynq

The IP is attached here.

 

The question is this implementation of AXI Streaming (FSL equivalent) enough to work with the AXI DMA.

This autogenerated IP only has TDATA, TREADY, TVALID and TLAST. 

Where as I think the AXI DMA has been design with complete AXI streaming interface for data packet that spans multiple blocks. TKEEP, TSTRB, TID and etc are not used here. C protocol for both is set as GENERIC.

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Adventurer
Adventurer
6,198 Views
Registered: ‎10-24-2007

Re: AXI DMA with custom AXI streaming IP in Zynq

AXI DMA asserts DMAIntErr when it compares the number of received bytes to the number set in the memory mapped register. How AXI DMA calculate the number of received bytes from S2MM AXI Streaming interface. 

 

Is it the number of bytes received from the first TValid asserted (1st after the previous Tlast) and until next Tlast.? In that case a simple streaming IP(only with TDATA, TREADY, TVALID and TLAST) cannot be connected easily to a AXI DMA. Is there a example of working AXI Streaming Master and slave IP that works with the AXI DMA?

 

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Adventurer
Adventurer
6,182 Views
Registered: ‎10-24-2007

Re: AXI DMA with custom AXI streaming IP in Zynq

For anyone's infomation, the issue was solved by asserting TLast on the S2MM channel on the transfer of the last byte/word.

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Visitor aslam_09pu
Visitor
2,716 Views
Registered: ‎11-01-2015

Re: AXI DMA with custom AXI streaming IP in Zynq

can you please send you custom ip here

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Highlighted
Visitor eepro_bt
Visitor
532 Views
Registered: ‎08-27-2018

Re: AXI DMA with custom AXI streaming IP in Zynq

Thanks a million.

12 years later, you really saved me from this problem before it kills me.

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