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Explorer
Explorer
9,620 Views
Registered: ‎07-13-2010

AXI Ethernet Lite and MII_to_RMII v1.01a problem

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Hello.

I want to use MII_to_RMII v1.01a core between AXI Ethernet lite and RMII PHY. I connect everything accordingly to it's datasheet p2. When run synthesis I get error, described in this AR# 35985 (note that I'm using AXI system, not PLB). However, even after making AXI Ethernet Lite IP local and commenting out unnecessary lines from .tcl file, I still get the same error: 

 

INFO: The Generic_Ethernet_10_100 core has constraints automatically generated
by XPS in
implementation/generic_ethernet_10_100_wrapper/generic_ethernet_10_100_wrapper.u
cf.
It can be overridden by constraints placed in the system.ucf file.

ERROR:EDK - xget_value  name : a null handle was provided
ERROR:EDK - Generic_Ethernet_10_100 (axi_ethernetlite) - expected integer but
   got "" 
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_1_proc_sys_reset_0_wrapper.ngc] Error 2
Done!

 With the PLB system, the applied solution works very well, but unfortunately not with AXI...Any ideas how I could solve this problem? In v1.01a datasheet there is nothing mentioned about support for AXI Ethernet Lite, so..maybe MII_to_RMII v1.01a isn't compatible with it at all..?

 

Ignas

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Observer ole2
Observer
12,772 Views
Registered: ‎12-24-2009

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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set  PARAMETER C_INCLUDE_PHY_CONSTRAINTS = 0
for each instance of axi_ethernetlite and all direct PHY mess hardcoded in the axi_ethernetlite_v2_1_0.tcl will be bypassed.

View solution in original post

16 Replies
Explorer
Explorer
9,600 Views
Registered: ‎07-13-2010

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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The only workaround I've found (at least for now it looks like it will be ok) is to use AXI to PLB bridge IP core, and then connect XPS Ethernet Lite core, which is definitely supported by the MII_to_RMII v1.01a IP core.

 

However, I'm still interested if there is a way to use MII_to_RMII v1.01a directly connected to AXI Ethernet Lite.. :)

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Observer ole2
Observer
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Registered: ‎12-24-2009

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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set  PARAMETER C_INCLUDE_PHY_CONSTRAINTS = 0
for each instance of axi_ethernetlite and all direct PHY mess hardcoded in the axi_ethernetlite_v2_1_0.tcl will be bypassed.

View solution in original post

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Explorer
Explorer
9,566 Views
Registered: ‎07-13-2010

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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Omg..it works!

Thank you so much Ole! 

I hope I'll be able to test it on the hardware on Monday to if it communicates with the phy properly, because I had some issues using the method I mentioned before..

 

Anyway, thanks a lot again :)

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Visitor zhdxaut
Visitor
9,519 Views
Registered: ‎10-11-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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do you test the approach above?

I use axi ethernet lite and rmii1.01a in XPS13.4,also set  PARAMETER C_INCLUDE_PHY_CONSTRAINTS = 0,

finally Bitstrream and Netlist be ok,and export the SDK.

But in the SDK,I use the perialtest  project  to test the ethernet loopback, it is fail.

Does it  mean rmii1.01 unsupport the axi ethernetlite ?I test the XPS ethernetlite and Rmii1.01,it is OKAY.

Do you have correct solution or support the refrence project to me by email:zhdcg@163.com?

Thank you very much!

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Explorer
Explorer
9,508 Views
Registered: ‎07-13-2010

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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Use attached project as a reference project.

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Visitor zhdxaut
Visitor
9,496 Views
Registered: ‎10-11-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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Thank you!

I compared your project to my project,they are same.But the problem is that ISE export SDK and BitStream is succeed,the project in SDK's test is failed.How do you verify your project in your SDK?and there is a problem in your project that there is not a timer for etherlite in your design.

I use The Xilinx C project Template "Peripheral Tests" program tested my and your project in SDK,also get the red line info.It meaned the loopback test in Ethernet_10_100_Lite failed.I test another PLB project ,it is passed.I think the mii_rmii_1.01v doesn't support axi_ethernetlite, and in vivado's IP list,there is a IP called mii_rmii_2.01v whose PDF datasheet states support axi_ethernetlite.My device is Spartan6, it can't use vivado.Maybe I would use PLB project for rmii and ethernetlite.

 

---Entering main---

 Running IntcSelfTestExample() for microblaze_0_intc... IntcSelfTestExample PASSED Intc Interrupt Setup PASSED

Running GpioOutputExample() for LEDS... GpioOutputExample PASSED.

Running GpioInputExample() for Node_Switches... GpioInputExample PASSED. Read data:0x1

Running UartLiteSelfTestExample() for debug_module... UartLiteSelfTestExample PASSED

 Runnning SpiSelfTestExample() for SPIFLASH... SpiSelfTestExample PASSED

 Running TmrCtrSelfTestExample() for axi_timer_0... TmrCtrSelfTestExample PASSED

 Running Interrupt Test  for axi_timer_0... Timer Interrupt Test PASSED

Running EmacLitePolledExample() for Ethernet_10_100... EmacLite Polled Example FAILED

---Exiting main---

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Visitor zhdxaut
Visitor
9,492 Views
Registered: ‎10-11-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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and , I am interested in your solution of "AXI to PLB bridge IP core, and then connect XPS Ethernet Lite core“。I tried it ,but it doesn't work.

Also,"However, I'm still interested if there is a way to use MII_to_RMII v1.01a directly connected to AXI Ethernet Lite.. :)"

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Explorer
Explorer
9,487 Views
Registered: ‎07-13-2010

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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I've also used peripheral test application to test axi ethernet lite and it passed the test (I haven't played with it further, though), so first of all (assuming you've already made proper hardware changes for your board), you have to find out which line or lines causes your periph test to fail and then you might be able see WHY it fails. 

 

And why do you want a timer for ethernetLite? 

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Visitor zhdxaut
Visitor
9,470 Views
Registered: ‎10-11-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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can you give a project of your test program in SDK? I want to compare it to mine.If there is not a timer in design ,the ethernetlite program testig can't run in SDK,especially use lwip test.

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Visitor zhdxaut
Visitor
4,967 Views
Registered: ‎10-11-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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and , I am interested in your solution of "AXI to PLB bridge IP core, and then connect XPS Ethernet Lite core“。

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Explorer
Explorer
4,952 Views
Registered: ‎07-13-2010

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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I 've just tested peripherals with autogenerated C project (did not use LwIP). I don't think so, that by comparing autgenerated C projects you'll find much useful info. Anyway, you'll find archive attached

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Observer emu
Observer
3,333 Views
Registered: ‎11-05-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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I actually have a similar problem on vivado 2015.3. I have a "working" design in vivado 2015.2, which had

some warning on the eth_lite/MII<>RMII, but now, it fails to route, as the automatic contraints made

are failing, because it likes to place the signals into the IOBs itself. Is the a way to ignore them?

 

Or, actually that xilinx finally implements the RMII interface into the IP?

Please?

;-)

 

 

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Observer emu
Observer
3,315 Views
Registered: ‎11-05-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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It really comes from the generated files :(

 

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Xilinx Employee
Xilinx Employee
3,306 Views
Registered: ‎02-06-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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Hi

 

The warnings on the clock will be caused if there is hierachy mismatch or renaming done in your design and this doesn't cause issue with the implementation.

 

Can you track the constraint which is causing the invalid constraints warning as this can cause error in implementation and disable the IOB true constraints in that XDC file and check if that helps.

Regards,

Satish

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Observer emu
Observer
3,300 Views
Registered: ‎11-05-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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What I really don't understand, is, that it is all generated ...

 

It complains about the clock, which is coming from the clock wizard block, the complains are about those two lines:

 

set_max_delay -from [get_cells -hierarchical -filter {NAME =~*I_TX_FIFO*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*I_TX_FIFO*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_a]
and
set_max_delay -from [get_cells -hierarchical -filter {NAME =~*I_RX_FIFO*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*I_RX_FIFO*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_b]

 

and the pins coming out of the module are I/O pins on the chip (besides of the interrupt line)

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Observer emu
Observer
3,282 Views
Registered: ‎11-05-2013

Re: AXI Ethernet Lite and MII_to_RMII v1.01a problem

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What is also funny on it.

It shows errors. but generates .bit and .bin files anyway ...

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