01-14-2013 01:29 PM
Hi, I am using the AXI IIC core as a master to communicate with a slave that throttles (clock stretches) after the address byte is received and before the first byte is transfered by the master. In other words, my external slave holds the clock line low after ACKing the address byte until it is ready to either receive or send data (depending on if its a R or W transfer).
I hooked up a logic analyser and it appears as though the AXI IIC core in master mode doesn't wait for my slave to be ready and simply proceeds trying to send (or receive) data after sending the IIC address byte.
Note: I'm using the non-dynamic polled driver version 2.04a. Also I have another example where there are 2 missing cycles (my slave throttles less). And another note, the slave is actually another FPGA running an older version of the core (XPS IIC) in slave mode. Our external Aadrvark IIC debugger has no issues talking to the slave and obeys the throttling / clock stretching done by the slave.
I'm considering starting a webcase about this.
08-15-2013 07:33 AM
This issues has been addressed and a CR was filed for a fix.
I believe this is to be fixed in v14.6/2013.3 with v2.07 of the AXI IIC driver.
08-28-2015 06:31 AM
I'm working with version 2.08a of the AXI IIC driver, but I have the same problem: the IIC core in master mode seems to not respect the throttling of the slave.
Do you have any idea?
09-02-2015 01:26 AM
Perhaps this function (AXI IIC acting as a master and detecting clock stretch forced by a slave device) is not supported by the microblaze's IP core?
01-15-2018 07:58 AM
Is this issue already fixed?
I am planning to use the most recent version of the AXI IIC core (as delivered with Vivado 2017.4) in my design and I would require support for clock stretching (the AXI IIC core would be the master and a slave device holds SCL low while it prepares read data). According to this post the AXI IIC core does not support clock stretching by slaves, so I could obviously not use it if the issue is not fixed.
02-07-2018 12:38 AM
I tested this on HW and obviously the issue is fixed. I ran my test with Vivado 2017.2.
02-07-2018 02:58 AM
Thanks for the update.
If possible please share your testcase for me to verify at my end as well.
02-15-2018 10:32 PM
My test-case is built on custom specific hardware including the I2C slave, so I guess it is not something you can easily reproduce.
However, I think it should be very easy to emulate an I2C slave that stretches the clock by adding a little logic to the scl_i line.
02-22-2018 07:34 AM
You mean to add in RTL top level wrapper or software application thru API.
02-28-2018 01:02 AM
Yes. Or you just attach a real I2C device that is known to do clock stretching.