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Visitor tobi1990
Visitor
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Registered: ‎04-25-2018

AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Hello,
after upgrading form Vivado 2018.1 to 2018.3
I had to realize that the AXI interconnect (2.1 Rev. 19) under Vivado 2018.3 does not work with different master / slave clocks.
To analyze, I have installed a System ILA and found that in a read access not even the ARready signal is set.

If the clocks on both sides are equal it works perfectly normal.

Unfortunately, I found nothing on the net for this bug.
Is this error already known to Xilinx?

best regards

Tobias Vogt

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Visitor tobi1990
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Registered: ‎04-25-2018

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Joe Thanks a lot for your hints.
I already tried to make a completely new design but it also do not work. I use many IP´s and the 18.3 have much problems handling IP´s.
I will try a new project without Block Design but this week I am on bussines trip.
regards

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Hello @tobi1990,

I have a couple questions about your configuration:

  1. Can you upload a screenshot of your configuration so we can see exactly what you are changing?
  2. What are the clocks that you are using, both with only 1 clock and with 2 clocks?  Where are they coming from?
  3. Are you using a Windows or Linux machine?
  4. If you have an ILA on the AXI Interconnect, can you send an ILA trace of the signals going in and out of that Interconnect?  You can add more traces if you feel that would be helpful.
  5. Have you tried removing the interconnect and placing another in its place?  Sometimes there have been issues when performing upgrades between versions of different IP.  If that still works, maybe trying to reinsert the other components in your design just to make sure that the upgrade process wasn't an issue.
  6. Though this sounds like a hardware issue, what software are you running?  Would you be able to run an example design (a screenshot of the other things going on in the design would show what example would be good to run)?  (Examples can be found on Windows at C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\<IP>\examples)

Thanks,

Caleb

Thanks,
Caleb
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Visitor tobi1990
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Registered: ‎04-25-2018

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Hello,

thanks for your answer.

Here my additional infos:

1/2.

clk Master AXI = 100MHz

clk Slave AXI = 50MHz

3. using Windows 10

4. sorry I didn't save any trace

5. already tried removing and placing a new AXI interconnet

I hope this helps

regards

Tobias Vogt

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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That is interesting.  If possible could I still get a screenshot of your design?  And if you could run again with the ILA that would be really useful.

In the meantime I hope to recreate the issue you are seeing.  By the way are your clocks coming from the PS?

Thanks,

Caleb

Thanks,
Caleb
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Scholar jg_bds
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Registered: ‎02-01-2013

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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A quick question about the 50- and 100-MHz clocks: are they traceable to the same source? e.g., If they're being generated from one or two MMCM/PLL's that both use the same reference clock, the answer would be 'yes'.  If one is being generated by an MMCM/PLL using one reference clock, and the other is coming from an MMCM/PLL that uses a different reference clock, the answer would be 'no'.

-Joe G.

 

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Visitor tobi1990
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Registered: ‎04-25-2018

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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the clocks PL0 and PL2 are 100MHz generated from IOPLL and the 50MHz generated by clk_wiz_0 sourced by PL2.

so yes it's traceable.

I also added a screen shot of my AXI construct.

regards

Tobias

AXI.PNG
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Visitor tobi1990
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Registered: ‎04-25-2018

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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AXI_interconnect_0 is the one with different source clocks
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Scholar jg_bds
Scholar
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Registered: ‎02-01-2013

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Ok. The clocks are even multiples of each other and are traceable to the same source, so we should have a synchronous system here.

Before we proceed, please fix the crossbar resets of the AXI Interconnects. This probably isn't the underlying problem, but we should get on a firm, basic footing to begin.

The ARESETN input of Interconnect IPs needs to be driven by the interconnect_aresetn output of your Processor System Reset block (sys_reset_clk1). Here's an example:

2019-02-05_7-32-44.jpg

I'm assuming sys_reset_clk1 is clocked by your 50-MHz clock. I further assume that all of the master and slave ARESETN inputs to both AXI Interconnects are driven by the peripheral_aresetn output of sys_reset_clk1.

Once that's done, please also share the configurations of your AXI Interconnects. You might also expand each interconnect (the [+] in the upper left corner) and share its structure.

-Joe G.

P.S. Why 2 separate 100-MHz output from the PSU?  Are they separated by phase?

 

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Scholar jg_bds
Scholar
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Registered: ‎02-01-2013

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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I think I bungled my description of how the resets should be done. This is what I was trying to get to:

2019-02-05_13-15-21.jpg

Haven't had a chance yet to look further at this.

-Joe G.

 

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Scholar jg_bds
Scholar
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Registered: ‎02-01-2013

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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So I finally had a chance to try this on an ZCU102.

I changed my BD a wee bit to allow for a non-Lite AXI transaction (to a BRAM):

2019-02-05_18-22-16.jpg

I used XSCT to initiate a couple of bus transactions:

2019-02-05_18-21-39.jpg

And I captured (most) of the read--on both sides of the second AXI Interconnect:

2019-02-05_18-22-52.jpg

2019-02-05_18-31-59.jpg

So there doesn't seem to be an intrinsic problem with AXI reads across clock domains in 2018.3.

Perhaps a problem was introduced when you updated your design from the earlier version. My design was freshly cobbled up within 18.3.

-Joe G.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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@tobi1990

Since @jg_bds was able to create a design with the same two clock domains with Vivado 2018.3, would you be willing to try rebuilding your design fresh in Vivado 2018.3?

As well, continueing with jg_bds' suggestion about fixing the resets would be smart.

If either of those steps fix your problem, it would be great if you could let us know, or respond with what results you get from these two steps if that does not work.

Thanks,

Caleb

Thanks,
Caleb
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Visitor tobi1990
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Registered: ‎04-25-2018

Re: AXI Interconnect Bug with different clock rates on Master/Slave in 2018.3

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Joe Thanks a lot for your hints.
I already tried to make a completely new design but it also do not work. I use many IP´s and the 18.3 have much problems handling IP´s.
I will try a new project without Block Design but this week I am on bussines trip.
regards

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