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Registered: ‎11-21-2013

AXI Interconnection Enable DATA FIFO, Why and How?

Hi, Everyone,


Basically i want to use AXI3/4 Interconnection to move data between DDR from/to PL in ZYNQ SoC.


I have a hard time understanding the option to enable DATA FIFO in AXI Interconnection IP,  as i can only find documents stating how to enable DATA FIFO for 32 depth or 512 depth (packet mode).


And a snipshot of information i got here: https://www.xilinx.com/support/answers/62785.html


However i don't know the purpose of why i should enable this option,  how does this option influences the communication signals (AXI Read/Write channels),  and the performance?


I appreciate if someone could explain or point me links to help me understand my doubts.

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