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Visitor
Visitor
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Registered: ‎01-28-2018

AXI SPI output ports

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I am using Vivado for a ZED board, and  have added the PS7 and AXI SPI blocks.  I want a single SPI master,so selected standard mode.  The wrapper shows more ports than I expected:

 

module spisystem_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
spi_rtl_io0_io,
spi_rtl_io1_io,
spi_rtl_ss_io);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout spi_rtl_io0_io;
inout spi_rtl_io1_io;
inout [0:0]spi_rtl_ss_io;

wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire spi_rtl_io0_i;
wire spi_rtl_io0_io;
wire spi_rtl_io0_o;
wire spi_rtl_io0_t;
wire spi_rtl_io1_i;
wire spi_rtl_io1_io;
wire spi_rtl_io1_o;
wire spi_rtl_io1_t;
wire [0:0]spi_rtl_ss_i_0;
wire [0:0]spi_rtl_ss_io_0;
wire [0:0]spi_rtl_ss_o_0;
wire spi_rtl_ss_t;

IOBUF spi_rtl_io0_iobuf
(.I(spi_rtl_io0_o),
.IO(spi_rtl_io0_io),
.O(spi_rtl_io0_i),
.T(spi_rtl_io0_t));
IOBUF spi_rtl_io1_iobuf
(.I(spi_rtl_io1_o),
.IO(spi_rtl_io1_io),
.O(spi_rtl_io1_i),
.T(spi_rtl_io1_t));
IOBUF spi_rtl_ss_iobuf_0
(.I(spi_rtl_ss_o_0),
.IO(spi_rtl_ss_io[0]),
.O(spi_rtl_ss_i_0),
.T(spi_rtl_ss_t));
spisystem spisystem_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.spi_rtl_io0_i(spi_rtl_io0_i),
.spi_rtl_io0_o(spi_rtl_io0_o),
.spi_rtl_io0_t(spi_rtl_io0_t),
.spi_rtl_io1_i(spi_rtl_io1_i),
.spi_rtl_io1_o(spi_rtl_io1_o),
.spi_rtl_io1_t(spi_rtl_io1_t),
.spi_rtl_ss_i(spi_rtl_ss_i_0),
.spi_rtl_ss_o(spi_rtl_ss_o_0),
.spi_rtl_ss_t(spi_rtl_ss_t));
endmodule

 

Going to the AXI Quad SPI v3.2 document, pages 19 and 20 indicate that sck_o, io0_i, and io0_o should correspond with SCLK, MISO, and MOSI.  The document appears to have a typo for the io0_i definition (says MOSI rather than MISO).  Also, why does the generated wrapper have ports that are not used in the standard mode?  Where is sck_o?   I need to constrain the pin-outs on the SCLK, MISO, and MOSI and get rid of the superfluous signals.  Can someone help me out?

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Visitor
Visitor
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Registered: ‎01-28-2018

Re: AXI SPI output ports

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1.  Thanks for answer on start-up primitive.  That tripped me up.  Hopefully others who want AXI standard SPI with SCLK pinned out will benefit from my mistake and uncheck this box before wasting countless hours.

 

2.  I think you missed my point on the second comment.  I DID define the constraints pins for the four SPI ports connected to the PL fabric.  The irony was that the error message said that I did not!  Only when I added the ZED board .xdc constraint file (that pins down all the other I/Os) did I get a zero error condition!

 

Maybe you can tell me (and my friends) what Vivado does when we tell it at the beginning that we are using a ZED board.  It does not add an .xdc constraint file, but assumed that it was implied.  Only when actually adding the ZED constraint file along with the SPI constraint file are things happy.  The error message is certainly deceptive by being exactly the complement of what it should be saying!

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Community Manager
Community Manager
3,569 Views
Registered: ‎07-23-2012

Re: AXI SPI output ports

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In standard mode of AXI Quad SPI IP, data ports are uni-directional unlike in dual and quad modes. In other words, in standard mode, IO0 corresponds to MOSI and IO1 corresponds to MISO. That is the reason why you have IO0 and IO1 in the port definitions.

I don't see either port definition or mapping of SCK in the code snippet. I guess that you have driven this internally in the block diagram that's why you don't see it here. Please share the snapshot of your bd to validate this.
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Visitor
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Registered: ‎01-28-2018

Re: AXI SPI output ports

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I built the block diagram in the usual way with the PS7 block and AXI SPI block.  I configured the AXI SPI block in standard mode with the master box checked.  Nothing fancy, just auto connected and then generated a wrapper.  I expected to see just the three SPI lines in the wrapper along with the DRAM lines.  Did I miss something?  Do you want to see an image of my block diagram?  Why should something so simple go so wrong?

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Registered: ‎07-23-2012

Re: AXI SPI output ports

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To me the wrapper looks fine except that SCK ports are missing. As mentioned earlier, if you are driving SCK port internally (in the block design), it is expected that you don't see it.
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Visitor
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Re: AXI SPI output ports

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Attached is a block diagram.  It consists of a PS7 and AXI quad SPI configured as a standard mode master.  It connects and validates.  The system is clocked by the main 100 MHz system clock.

 

The generated wrapper show extra ports and no master SCLK output.   How to fix so only two outputs and one input (SCLK, MOSI, MISO)?

axi spi block diagram.png
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Visitor
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Re: AXI SPI output ports

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Attached is implemented schematic for the axi quad spi block.  If this is a single standard mode master SPI, then why are the other ports showing up?

axi spi schematic.png
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Re: AXI SPI output ports

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The following are the ports that comes out of AXI Quad SPI IP when configured in standard mode-
1. Master Out Slave In (MOSI)-> IO0 and this IOB acts like output only.
2. Master In Slave Out (MISO)-> IO1 and this IOB acts like input only.
3. SCK-> This is an output port as AXI Quad SPI IP is configured in master mode.
4. Slave Select ports- SS.

In your design, you have instantiated a STARTUP primitive inside IP so SCK_O will be routed to the STARTUP primitive and the clock of the flash will be driven by the STARTUP primitive.

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Visitor
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Re: AXI SPI output ports

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I unchecked the AXI Quad SPI box for "enable STARTUP primitive" and now see the SCLK signal.  I have set pin constraints on the four signals.  Still I get an error.  What do I need to do to clear this error?  See attached I/O and error message.

axi spi error message.png
axi spi io.png
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Re: AXI SPI output ports

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How ironic:  the error message suggests that there is a problem with the 4 ports associated with the AXI SPI block.  Instead, the complement was actually the problem!  I thought that specifying the ZED board would be sufficient to constrain the board pins.  Instead, I had to add zedboard_master_XDC_RevC_D_v3.xdc to my constraints to remove the errors!  It appears it was all signals but the SPI signals that were the problem!  I now compile the bit stream without errors.

 

So this leaves two questions:

1.  What is the purpose of "enable STARTUP primitive" box and why is it checked by default?  It would seem that anyone using SPI would want the SCLK signal or why bother?  I suggest in future updates that the default state is unchecked for this box.

2.  Why was the error message so deceptive?  It told me that I had problems with SPI pin definition when in fact it was really complaining about not defining all the other pins!  Does not compute!

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Registered: ‎07-23-2012

Re: AXI SPI output ports

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#1. When you use SPI flash for both configuration and post-configuration storage, we use a STARTUP primitive. The primary purpose of using a STARTUP primitive is to source clock to the flash memory. You can find more details about STARTUP primitive in UG470.
Most users use the flash memory for storing both configuration and user data. Hence, startup primitive is enabled by default.

#2. ZED board doesn't have a SPI flash connected to the PL section. Hence, it's not part of the board xml file. You see the error because you haven't manually configured the IO standard for these IO ports. Vivado expects the user to provide location and IO standards for all the ports.
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Re: AXI SPI output ports

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1.  Thanks for answer on start-up primitive.  That tripped me up.  Hopefully others who want AXI standard SPI with SCLK pinned out will benefit from my mistake and uncheck this box before wasting countless hours.

 

2.  I think you missed my point on the second comment.  I DID define the constraints pins for the four SPI ports connected to the PL fabric.  The irony was that the error message said that I did not!  Only when I added the ZED board .xdc constraint file (that pins down all the other I/Os) did I get a zero error condition!

 

Maybe you can tell me (and my friends) what Vivado does when we tell it at the beginning that we are using a ZED board.  It does not add an .xdc constraint file, but assumed that it was implied.  Only when actually adding the ZED constraint file along with the SPI constraint file are things happy.  The error message is certainly deceptive by being exactly the complement of what it should be saying!

View solution in original post

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