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Observer vjerbic
Observer
7,238 Views
Registered: ‎04-08-2011

AXI-Stream FIFO 64bit Read

Hello,

 

I am using AXI Stream FIFO configured to have AXI4-Lite Interface for configuring registers, AXI4-FULL for access to data and Receive AXI Stream Interface for storing data from external ADC. (Screenshot attached)

 

Data Bus Width is 64 bit(Concatenated 16bit data of 4 ADC Channels).

 

AXI-Lite and AXI4-FULL interfaces are connected through AXI Interconnect to Zynq S_AXI_GP0.

Since AXI4FULL is 64bit wide, Data Width converter is automatically implemented in AXI interconnect IP.

 

I am using following code to initialize FIFO(Code is copied form Xilinx Polling Example)

 

int XLlFifo_Setup(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int Error;
Status = XST_SUCCESS;

/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}

/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}

/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}

return Status;
}

 

I check for available words by XLlFifo_iRxOccupancy function. When FIFO is ful,l I try to read data and problem appears.I try to read data with following section

 

Status = XLlFifo_iRxOccupancy(&FifoInstance);
xil_printf("FIFO Occupancy %d \n\r", Status);
for (j=0;j<Status;j++){

RegFifo = *(volatile long long *) (FifoInstance.Axi4BaseAddress + AXI4_FULL_RDFD_OFFSET);
xil_printf("%d %d %d %d\r\n",(s16) (RegFifo & 0x000000000000FFFF),(s16) ((RegFifo>>16) & 0x000000000000FFFF),(s16) ((RegFifo>>32) & 0x000000000000FFFF),(s16) ((RegFifo>>48) & 0x000000000000FFFF));
}

 

With this code I get only every second sample, so I cannot read whole FIFO content.

 

When I use following code

 

for (j=0;j<Status;j++){

RegFifo = *(volatile u32 *) (FifoInstance.Axi4BaseAddress + AXI4_FULL_RDFD_OFFSET);
xil_printf("%d %d\r\n",(s16) (RegFifo & 0x0000FFFF),(s16) ((RegFifo>>16) & 0x0000FFFF));
}

 

I get every sample but only for lower 32bits of AXI-Stream which is 64bits wide.

 

What should I use to get whole content of FIFO?

Is AXI Stream FIFO meant to be used in that way?

 

Kind regards,

Vedran

 

 

 

 

Screenshot 2015-10-16 14.10.52.png
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2 Replies
Newbie jdecesare
Newbie
500 Views
Registered: ‎01-18-2019

Re: AXI-Stream FIFO 64bit Read

Was there ever a solution to this? I am having a similar problem.  

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440 Views
Registered: ‎07-27-2015

Re: AXI-Stream FIFO 64bit Read

I have the same if not a similar problem, I am looking at this link right now:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Issue-with-AXI-Stream-Fifo-with-AXI4-full-and-64-bit-mode/td-p/791153

Once I figure it out I'll write it up and push to github

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