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Adventurer
Adventurer
3,603 Views
Registered: ‎07-19-2012

AXI_USB2_Device, using open open ip example design in existing project

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Hello,

 

I'd like to implement a USB in an existing design I have, I havn't implemented my own USB interface before and I'm looking for the path of least resistance.

After looking at fig 6-1 on page 55 of this document:

http://www.xilinx.com/support/documentation/ip_documentation/axi_usb2_device/v5_0/pg137-axi-usb2-device.pdf

I think I can remove or modify the ATG Lite Agent and instantiate the top module in my existing design.

I think this is advantagous because the IP example includes an implementation of the ULPI/HSIC driver. 

 

My questions are:

1) Is it possible to do this by intantiating the _exdes.v top module on the existing system wrapper I have in my existing block design? (is it possible to do this at all)

2) Does what I have outlined make sense? Does any one have any adivice or recomendations for me?

 

Thank you! Any replies are very appreciated!

 

Sam

 

 

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Scholar trenz-al
Scholar
4,880 Views
Registered: ‎11-09-2013

Re: AXI_USB2_Device, using open open ip example design in existing project

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UART is not a BUS it is async serial interface, if you send data over USB UART, then it is transmitted delayed and in chunks, and the latencies are large.

 

so "sync UART to BRAM" seems like something wrong in the initial concept. you can sync to uart data available but that is normally of no use

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Registered: ‎11-09-2013

Re: AXI_USB2_Device, using open open ip example design in existing project

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Did you check the IP Core license fees? Are they acceptable for you?

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Adventurer
Adventurer
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Registered: ‎07-19-2012

Re: AXI_USB2_Device, using open open ip example design in existing project

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I have not checked and just realized it's not included in my Xilinx license, I noticed that the IP supports evaluation,

I'm hoping that the evauluation feature will let me use the IP core enough to determine if purchasing the license is justifiable.

 

The reason I'm trying to use USB is because the default UART 7Z010 (microzed board) I'm using to read data out to the terminal does not appear to have any signals I can use to syncronize my data with the UART bus. I'm using a dual port BRAM and want to syncronize the timing of my read address with the UART.

Any Advice for accomplishing this task?

 

Thanks

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Adventurer
Adventurer
3,590 Views
Registered: ‎07-19-2012

Re: AXI_USB2_Device, using open open ip example design in existing project

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I've requested a quote for the ip license and downloaded the 120 day evaluation license

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Scholar trenz-al
Scholar
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Registered: ‎11-09-2013

Re: AXI_USB2_Device, using open open ip example design in existing project

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UART is not a BUS it is async serial interface, if you send data over USB UART, then it is transmitted delayed and in chunks, and the latencies are large.

 

so "sync UART to BRAM" seems like something wrong in the initial concept. you can sync to uart data available but that is normally of no use

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Adventurer
Adventurer
3,558 Views
Registered: ‎07-19-2012

Re: AXI_USB2_Device, using open open ip example design in existing project

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Thank you,
I'm new to embedded software obviously.
I'm working on implementing the USB0 and using the Microzed in device mode. I think memory mapping may be a robust solution for data synchronization
-Sam
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