UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
369 Views
Registered: ‎01-07-2014

AXI VIP: AWready/ Wready gating

Jump to solution

Hello,

 I simulate my design (that has AXI3 master write channel) against AXI VIP module. AXI VIP is configured as Read/Write. 

I want to do 32 bursts (16-beat each, 64bit data bus, for a 4KB of data to the addr. 0x1800_0000) from my AXI3 master to AXI VIP and check that data.I observe that everything starts ok, no errors are reported: 

INFO: [slave vip agent_wr_driver] (axi_vip_pkg.axi_slv_wr_driver(C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0)::aw_channel.AW_CHANNEL) 11535000 : AWVALID >>>
XIL_AXI_WRITE (71) A:0x0000000018000000 ID:0x00000000 len:0x0f XIL_AXI_SIZE_8BYTE XIL_AXI_BURST_TYPE_INCR C:0b0000 L:XIL_AXI_ALOCK_NOLOCK P:0b000<<<
.....
INFO: [slave vip agent_wr_driver] (axi_vip_pkg.axi_slv_wr_driver(C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0)::w_channel.W_CHANNEL) 11995000 : W LAST -- write_beat     Last:1 D:0x001200ff50502134 BE:0b11111111
 
INFO: [slave vip agent_wr_driver] (axi_vip_pkg.axi_slv_wr_driver(C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0)::push_reactive_q) 11995000 : PUSH_REACTIVE_Q: PUSH (         0) >>> XIL_AXI_WRITE (71) A:0x0000000018000000 ID:0x00000000 len:0x0f XIL_AXI_SIZE_8BYTE XIL_AXI_BURST_TYPE_INCR C:0b0000 L:XIL_AXI_ALOCK_NOLOCK P:0b000 <<<
.......
 
However, at the end of 16th burst, the 17th does not start : AWREADY and WREADY are stuck at zero (as shown). There's a log message pointing to WREADY_POLICY_GATING: 
 
INFO: [slave vip agent_wr_driver] (axi_vip_pkg.axi_slv_wr_driver(C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0)::push_reactive_q) 19195000 : PUSH_REACTIVE_Q: PUSH (        15) >>> XIL_AXI_WRITE (216) A:0x0000000018000780 ID:0x00000000 len:0x0f XIL_AXI_SIZE_8BYTE XIL_AXI_BURST_TYPE_INCR C:0b0000 L:XIL_AXI_ALOCK_NOLOCK P:0b000 <<<
 
INFO: [slave vip agent_wr_driver] (axi_vip_pkg.axi_slv_wr_driver(C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0)::wready_policy_gating.WREADY_POLICY_GATING) 19195000 : EXIT
 
I could not find anything related in the VIP documentation. 
Could anyone point me in the right direction, what happens here, why the VIP seems to be stuck in the middle of the operation? 
Thanks,
 
 
 
AXI_wready_gating.png
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
304 Views
Registered: ‎10-04-2016

Re: AXI VIP: AWready/ Wready gating

Jump to solution

Hi @dmgusev ,

I notice in your simulation waveform that there are no BRESPs coming back from the AXI VIP slave. Have you configured the AXI VIP to provide responses? From the warnings you are getting, it suggests that the queues for the incoming write transactions are getting full.

Please refer to the AXI VIP example designs for coding examples that provide basic BRESP/RRESP handling. 

Regards,

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
305 Views
Registered: ‎10-04-2016

Re: AXI VIP: AWready/ Wready gating

Jump to solution

Hi @dmgusev ,

I notice in your simulation waveform that there are no BRESPs coming back from the AXI VIP slave. Have you configured the AXI VIP to provide responses? From the warnings you are getting, it suggests that the queues for the incoming write transactions are getting full.

Please refer to the AXI VIP example designs for coding examples that provide basic BRESP/RRESP handling. 

Regards,

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
Contributor
Contributor
264 Views
Registered: ‎01-07-2014

Re: AXI VIP: AWready/ Wready gating

Jump to solution

Hi Deanna,

  Indeed, adding the function to send responses unblocked the situation. The one I used is like this: 

function automatic void fill_wr_reactive(inout axi_transaction t);

   t.set_bresp(XIL_AXI_RESP_OKAY); 
endfunction

Thanks,

0 Kudos