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Visitor lajitha82
Visitor
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Registered: ‎12-18-2018

AXI chip2chip

In our design , we would like to build 64bit AXI chip2chip interface between Kintex7 (XC7K70T-2FBG484I) and Zynq 7000(XC7Z030-1SBG485) with phy as SelectIO DDR. What are the interface signals needed including address, data and control lines to build the chip2chip interface in both master and slave.  

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