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Registered: ‎09-17-2018

AXI stream switch IP: multiple slaves and 1 master


I want to use the axi stream switch IP core to switch between 2 video sources, and I use 2 test pattern generators and 1 frame buffer write to test it. I enabled "Use control register routing" to select the slave through SW.

axis_switch_test.pngHowever, I found this IP only behaves normally when there is only one axi stream valid. The observed results are as follows:

  • when I only start tpg_0 and map SI[0] to MI[0], I can get frame interrupts. 
  • when I only start tpg_1 and map SI[1] to MI[0], I can get frame interrupts.
  • when I start both tpg_0 and tpg_1 and map SI[0] to MI[0], no frame received.
  • when I start both tpg_0 and tpg_1 and map SI[1] to MI[0], frames interrupts received

This is not disired result as I want to be able to switch between video streams without disabling either of them. 

Any idea on this? Thank you very much.



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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: AXI stream switch IP: multiple slaves and 1 master

Hi @xinyiz ,

To start to understand what is going on, I'd really need to see traces of the streaming ports into/out of the switch. Can you add an ILA to S00_AXIS, S01_AXIS and M00_AXIS?

I'd like to see captures of the four scenarios you describe. 



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