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Scholar beandigital
Scholar
735 Views
Registered: ‎04-27-2010

AXI traffic generator andchecker

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Hi

 

Do Xilinx provide IP that would generate AXI write and read requests and then compare the read data to the write?

Thanks

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Scholar hbucher
Scholar
822 Views
Registered: ‎03-22-2016

Re: AXI traffic generator andchecker

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@beandigital PG125

https://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v2_0/pg125-axi-traffic-gen.pdf

Check page 67

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Scholar hbucher
Scholar
823 Views
Registered: ‎03-22-2016

Re: AXI traffic generator andchecker

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@beandigital PG125

https://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v2_0/pg125-axi-traffic-gen.pdf

Check page 67

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
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Contributor
Contributor
352 Views
Registered: ‎10-29-2018

Re: AXI traffic generator andchecker

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Dear Sir,

I am simulating AXI Traffic Generator in Master Loopback mode without PS intervention. I have connected M_AXIS_MASTER to S_AXIS_MASTER. I have given the appropriate signal to clk and reset port. I have generated a high pulse at core_ext_stop and core_ext_start port. When I simulate the design, axis_err_count port is 0000. 

To check whether axis_err_count port is counting no. of errors properly, I corrupted the m_axis_1_tdata as follows and, then fed to s_axis_1_tdata:

assign s_axis_1_tdata_c = m_axis_1_tdata + 32'd10;

Still s_axis_err_count is 0000. Please suggest how to resolve this issue.

Further, I brought up all AXI stream data interface signal to the top Verilog module as port, then I simulated the design. I observed following in the simulation result:

1. m_axis_1_tvalid and s_axis_1_tready is never high. Please see below the attachment.  

Please help me out to sort the above issue.

Any help would be appreciated.

Thank you and Regards,

Puja Kumari

Capture.PNG
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