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Participant mnanoop2014
Participant
536 Views
Registered: ‎10-29-2018

AXI write transaction protocol implementation error

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Hi,
When I use the Xilinx's template AXI Slave code (with 64B memory) for simulation, I get a waveform like this for a write operation:XIL2.png

 When I use a verilog code generated out of chisel (after dealing with the active low reset changes) the waveform I get is like shown below:XIL1.png

 

PS read the following noting the difference between awready and AWREADY

From what I understand from reading about the protocol documentation and reading the template code, the second waveform that I have generated seems to be correct. 
An intermediate register (awready) is pulled high only when (~awr_awv_flag & ~arr_arv_flag & ~awready & AWVALID) is high. But since AWREADY (wired to awready) is channelled through a register, it should be changed in the next clock cycle after the said condition is passed. 

This is what is happening with my chisel generated code. Why is this not the case with Xilnx's template code? Even in there, the AWREADY is channelled through a register(named awready).

The problem I am facing with this is that when I initiate one write transaction from Zynq MPSoC, it writes to the register (or not) and then throws a AP time out error. Might this discrepancy be the source of the error or might that AP time out error be because of something else?


TIA,

Anoop

 

 

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Scholar jg_bds
Scholar
510 Views
Registered: ‎02-01-2013

Re: AXI write transaction protocol implementation error

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The AXI Spec says "The master can assert the AWVALID signal only when it drives valid address and control information. When asserted, AWVALID must remain asserted until the rising clock edge after the slave asserts AWREADY."

It appears that neither case is observing that requirement, since both are allowing a lingering AWVALID signal. The former case does seem to de-assert AWVALID before it leads to trouble. The latter case leaves it hanging out there--like a high breaking ball--until the slave notices it and thinks another transaction is starting.

-Joe G.

 

 

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Scholar jg_bds
Scholar
511 Views
Registered: ‎02-01-2013

Re: AXI write transaction protocol implementation error

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The AXI Spec says "The master can assert the AWVALID signal only when it drives valid address and control information. When asserted, AWVALID must remain asserted until the rising clock edge after the slave asserts AWREADY."

It appears that neither case is observing that requirement, since both are allowing a lingering AWVALID signal. The former case does seem to de-assert AWVALID before it leads to trouble. The latter case leaves it hanging out there--like a high breaking ball--until the slave notices it and thinks another transaction is starting.

-Joe G.

 

 

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