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Registered: ‎12-03-2014

AXI2 C2C Clocking issue

Hi I am starting design with AXI C2C master and slave I am using 1 Zync and 1 Artix-7 I am using 2 instance 1 AXI C2C master and 1 AXI C2C Slave in each FPGA As for the AXI C2C master the s_aclk is input and feed this input pll output 100Mhz So my questions are 1. what is the role of the m_aclk_out ? 2. does it sync to s_aclk? 3. Which clock is used to AXI interface signals ? s_aclk or m_aclk_out ? Tnx, Moshe
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Xilinx Employee
Xilinx Employee
Registered: ‎06-14-2012

Re: AXI2 C2C Clocking issue


For Independent Clock mode,all signals on the AXI Slave interface of an AXI Chip2Chip Master core are synchronous to s_aclk.
For Common Clock mode, all AXI Chip2Chip Master core operations are synchronous to s_aclk.


The m_aclk is always required as AXI input clocks for the AXI Chip2Chip Slave core. The
m_aclk_out is provided as an additional clock output in Common Clock mode. The
m_aclk_out output can be used as an AXI System Clock. In addition, it should be
connected to m_aclk input of the AXI Chip2Chip Slave core.


You will find all the detailed information on the product guide.




Hope this helps.




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