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Visitor qdeslandes
Visitor
215 Views
Registered: ‎10-21-2019

AXI4-Stream FIFO packet count

Hi,

I'm working on AXI4-Stream FIFO integration inside the Linux kernel. From the documentation, I can't tell how to know the number of packets received or the packet size on the receiving end. On read, the sequence is the following (described in the documentation):

- Read RDFO, which stores the number of 32bits words received during the last transaction. This register will return 0 as soon as RLR is read.
- Read RLR, stores the number of bytes to read from the device's memory
- Read RDR, the destination address
- Read the data from RDFD

If I receive 2 packets, RDFO will store the size (in 32bits words) of the last received one, and logically RLR will be set to:

packet1.size + packet2.size

Otherwise, if RLR stores the size of only 1 packet and reading it reset RDFO to 0, we would lose some packet information.

 

So, when receiving multiple packets, is there a way to know the size of the first / second / xth one received?

I could ensure to read a packet a soon as we receive a "packet received" interruption, but I can't tell the kernel will read RLR fast enough before the core receives another packet and update RLR with the size both packet.

Thank you!

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: AXI4-Stream FIFO packet count

Hi @qdeslandes ,

Please refer to Table 2-9 in PG080. If there is more than one packet in the FIFO, your register sequence will look like this:-

1. Read RDFO, which stores the number of 32bits words received during the last transaction. This register will return 0 as soon as RLR is read if there is only 1 packet in the receive FIFO. Let's call this packet 0.
2. Read RLR, stores the number of bytes to read from the device's memory. This corresponds to the number of bytes in packet 0.
3. Read RDR, the destination address
4. Read the data from RDFD

5. Re-read RDFO. If this is still 0, no more packets have been received. If this is not zero, another packet (packet 1) has come in and is ready to be received.

6. Repeat steps 2-4 to handle packet 1.

There is an example bare metal driver and application for this FIFO. It might be helpful to look at that code if you haven't already.

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo

Regards,

Deanna

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