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Visitor tuxtech
Registered: ‎01-06-2016

AXI4-Stream FIFO receive data from custom VHDL peripheral



i'm designing a system on a ZYNQ where a custom VHDL module sends data to an AXI4-Stream FIFO, which is connected via AXI4-Lite to a MicroBlaze:


VHDL-Module -----AXI4-Stream----AXI4-Stream FIFO-----AXI4-Lite-----MicroBlaze


I used the xllfifo_polling_example.c and successfuly sent data from the MicroBlaze to the Module by just shorting TREADY and TVALID of the FIFO block. Now I'm trying to let the MicroBlaze receive data. I set TVALID always to 1, waited for TREADY to become 1 and then assigned my 32-bit data to TDATA. When I run the MicroBlaze FIFO exampe, i get the folowing UART output:


--- Entering main() ---                                                         
 ERROR : Reset value of ISR0 : 0x4000000        Expected : 0x0                  
Axi Streaming FIFO Polling Example Test Failed                                  
--- Exiting main() ---

The ISR-REgister is cleared before and then read again and bit 26 is set. which means "Receive Complete / Interrupt pending".

Why does that error occur?


Is my approach correct or should i use the IP-Packager and create a new custom AXI4-Stream peripheral?


Thanks for your help.

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Visitor liudi
Registered: ‎03-01-2018

Re: AXI4-Stream FIFO receive data from custom VHDL peripheral


i want to send data from pc to fpga using ethernet communation,now i have created the block design with microblaze,and completed the ethernet communation and received the data,but i need to store the received data to DDR3,and i also need write the data from  DDR3 to a FIFO,but I don't know which kind of FIFO I need to add to the .bd and write C code in SDK to control the FIFO,is there any FIFO API I can use to realize my project.

Additionally, dose the code xllfifo_polling_example.c have any reference value for me ?



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