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1,476 Views
Registered: ‎07-14-2017

AXI4 full slave

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Hello,

 

   I have a full AXI slave peripheral that was generated from the Vivado Create and Package IP and follows the Xilinx template with my added logic. I would like to test the peripheral for burst transfers, and i have seen that i can use BFM or the newer AXI AVI for that.

  The thing is that they seem to complicated and the is not enough information on how to use them, is there an easier way to generate bus signals from burst transactions?

  Is something like this https://github.com/muzafferkal/axi-bfm/blob/master/axi3_master_bfm.sv suitable?

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: AXI4 full slave

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@kgkougkoulias Honestly I can't promise this IP would work in all cases. Unless you're willing to debug (and submit changes I hope so that I can't fix it), your time is probably better spent trying to learn the new Xilinx verification IP. I don't plan to make any independent fixes to my code as I plan to use the Xilinx one now that it doesn't need a license.
I hope you have seen this document: https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_0/pg267-axi-vip.pdf. It doesn't look too complicated.

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Teacher muzaffer
Teacher
2,366 Views
Registered: ‎03-31-2012

Re: AXI4 full slave

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@kgkougkoulias Honestly I can't promise this IP would work in all cases. Unless you're willing to debug (and submit changes I hope so that I can't fix it), your time is probably better spent trying to learn the new Xilinx verification IP. I don't plan to make any independent fixes to my code as I plan to use the Xilinx one now that it doesn't need a license.
I hope you have seen this document: https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_0/pg267-axi-vip.pdf. It doesn't look too complicated.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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1,330 Views
Registered: ‎07-14-2017

Re: AXI4 full slave

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OK, i will try to stick with Xilinx IP. 

 

Thanks for the help

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