UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant patolsky
Participant
231 Views
Registered: ‎05-07-2018

AXI4 stream interconnect dont output tvalid

Hi all,

I made a block design with axi4 stream interconnect.(vivado 2018.1)

You can see in the simulation, that I get on IP inputs valid and data but in the output of the IP I dont get valid, what can be the issue?

stream.jpg

Thanks,

Shai

0 Kudos
2 Replies
Moderator
Moderator
162 Views
Registered: ‎11-09-2015

Re: AXI4 stream interconnect dont output tvalid

Hi @patolsky 

This is strange because I would not expect the tlast to be transmitted if tvalid is not high.

Make sure you are resetting the AXI4-Stream interconnect for few clock cycles (I think it requires at least 16 clock cycle reset)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Participant patolsky
Participant
117 Views
Registered: ‎05-07-2018

Re: AXI4 stream interconnect dont output tvalid

Hi @florentw 

It works when I changed tdest high to 0xFFFF_FFFF .

My base tdest was 0x0000_0000 and the high was 0x0010_0000 and in the simulation the tdest was 0x02.

Only when I changed tdest high to 0xFFFF_FFFF it works.

Shai