We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Participant darin_i
Registered: ‎02-15-2018

Access to PHY gpio pins from PL on a PicoZed 7Z030 SOM

I just want to confirm that what I want to do is not possible (as seems to be indicated in UG585). I searched, but don't see anyone else in the forum who has tried this.


I would like to use the PHY provided on the PicoZed 7Z030 SOM instead of the PS GEM controller.


This would involve disabling the GEM (easy) and repurposing the gpio pins that the PHY is connected to (MIO 16:27, 52, 53) which seems to be not possible. To access these pins from the PL, I'd have to in some way route the EMIO access (through Block 2, 3 of the gpio array) to Block 0.


Can anyone confirm for me that this is not possible before I move on?



0 Kudos