02-05-2018 04:35 AM
I would like to access the DDR4 memory connected to the PS on a XCZU3CG device from the PL. I would like to store data coming through a MIPI-DPHY interface in the DDR4 memory, this data should later be read for further analysis also via the PL. The current board I'm targeting has DDR4 memory connected to the PS. How can I access that memory if this is even possible. Can the AXI-Master IPIF be used on this device?
02-05-2018 11:15 PM
The PS DDR controller is accessed as an AXI Slave, just like an AXI BRAM or other generic memory.
Yes, a master will eventually have to create a transaction, translating from one format into AXI transactions. I'm not familiar with that video format, but perhaps the AXI VDMA would be helpful?
02-06-2018 12:08 AM
The actual format of the video stream is not relevant to me at the moment. I want to transfer only the raw data stream and don't care about the content at the moment. I don't want to use the processor to do the data transfer.
I tried to use the axi_master_burst core to create transactions (PG162). How can I simulate the design? I'm new to FPGA / Embedded processors.
02-06-2018 05:55 PM
02-06-2018 11:41 PM
The throughput of the interface is not relevant for me at the moment. I am looking for a starting point of an implementation. The master_burst_core seemed to be a good one in my eyes. Anyway what would be the alternative in this case?