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844 Views
Registered: ‎02-05-2018

Accessing PS DDR from PL XCZU3

Hi,

 

I would like to access the DDR4 memory connected to the PS on a XCZU3CG device from the PL. I would like to store data coming through a MIPI-DPHY interface in the DDR4 memory, this data should later be read for further analysis also via the PL. The current board I'm targeting has DDR4 memory connected to the PS. How can I access that memory if this is even possible. Can the AXI-Master IPIF be used on this device?

 

Thanks

 

Sebastian

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-30-2007

Re: Accessing PS DDR from PL XCZU3

The PS DDR controller is accessed as an AXI Slave, just like an AXI BRAM or other generic memory.

 

Yes, a master will eventually have to create a transaction, translating from one format into AXI transactions. I'm not familiar with that video format, but perhaps the AXI VDMA would be helpful?

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Registered: ‎02-05-2018

Re: Accessing PS DDR from PL XCZU3

The actual format of the video stream is not relevant to me at the moment. I want to transfer only the raw data stream and don't care about the content at the moment. I don't want to use the processor to do the data transfer. 

I tried to use the axi_master_burst core to create transactions (PG162). How can I simulate the design? I'm new to FPGA / Embedded processors. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-30-2007

Re: Accessing PS DDR from PL XCZU3

I'm not sure that we suggest the master burst core for new designs. Which direction to use for a custom IP master will depend on the throughput, the management of the transfer, and the format of incoming data handshaking.
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Registered: ‎02-05-2018

Re: Accessing PS DDR from PL XCZU3

The throughput of the interface is not relevant for me at the moment. I am looking for a starting point of an implementation. The master_burst_core seemed to be a good one in my eyes. Anyway what would be the alternative in this case?

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