UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
6,175 Views
Registered: ‎11-21-2013

After setting slcr.FPGA_RST_CTRL for PL, what is the sequence of starting the FPGA application?

Jump to solution

Hi, Dear All,

 

I have a embedded design inclusing AXI DMA and a user IP, both of them are connecting though s_axilite to the arm processor in the ZYNQ PS.

 

Each time i ran the program in SDK, i have to reset the whole system by pusing the on-board botton and reprogram the FPGA if i want to ran the program again. So to avoid that, i am using slcr.FPGA_RST_CTRL for resetting the PL, so that i don't have to reload the bit file again theoretically.

 

    Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
    Xil_Out32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET, 0x01F33F0F);
    Xil_Out32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET, 0x01F33F00);
    status = Xil_In32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET);
    xil_printf("\r SLCR FPGA RST CTRL REG: %x", status);

 

With these code i can see in the Chipscope a 10 cycle length valid reset signal on FCLK_RESET0_N, however, after the reset i couldn't access any of the registers in the AXI DMA and the user IP, even the SLCR_0_* register shown above, the code just hangs on the statuse = Xil_In32(*). Or any other places when i try to access some registers.

 

Anyone know why is that? From my point of view, the FCLK_RESET0_N signal only resets the functions in the PL, so all the implementations as AXI DMA, s_axilite interconnect should be still working.

 

Thank you very much for any suggestions!

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
11,257 Views
Registered: ‎06-14-2012

Re: After setting slcr.FPGA_RST_CTRL for PL, what is the sequence of starting the FPGA application?

Jump to solution

Were they any pending AXI transactions when you reset? Resetting it this way might hang up the AXI Interconnect clock.

Make sure that they are not pending transactions from master or slave side and then do the reset.

 

Regards

Sikta

View solution in original post

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
11,258 Views
Registered: ‎06-14-2012

Re: After setting slcr.FPGA_RST_CTRL for PL, what is the sequence of starting the FPGA application?

Jump to solution

Were they any pending AXI transactions when you reset? Resetting it this way might hang up the AXI Interconnect clock.

Make sure that they are not pending transactions from master or slave side and then do the reset.

 

Regards

Sikta

View solution in original post

0 Kudos
Explorer
Explorer
6,168 Views
Registered: ‎11-21-2013

Re: After setting slcr.FPGA_RST_CTRL for PL, what is the sequence of starting the FPGA application?

Jump to solution

Thank you very much for your reply!

 

There indeed has AXI transactions going on when i reset the PL. So the design behaves like this:

 

at the beginning, 6 addresses are sent to the user IP though AXI DMA, afterwards the user IP which has a AXI4 Master interface is continuing checking to read/write from/to these 6 addresses. It won't stop on checking those addresses. But these connections are connected to S_AXI_HP and S_AXI_ACP ports.

 

Do you think this is the reason for the problem i mentioned? The problem i mentioned is related to the register access so that is in s_axi_lite interface which connects to M_AXI_GP port.

 

In addition, update the progress, for the code

    status = XAxiDma_ReadReg(XPAR_AXI_DMA_0_BASEADDR, 0x00); // control status
    xil_printf("\r Before resetting, AXI DMA MM2S CONTROL REG: %x\n", status);
    status = XAxiDma_ReadReg(XPAR_AXI_DMA_0_BASEADDR, 0x04); //  status
    xil_printf("\r Before resetting, AXI DMA MM2S STATUS REG: %x\n", status);

    Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
    Xil_Out32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET, 0x01F33F0F);
    for(i=0; i<10; i++)
    Xil_Out32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET, 0x01F33F00);

    for(i=0; i<1000; i++);

    status = Xil_In32(XPAR_PS7_SLCR_0_S_AXI_BASEADDR+SLCR_FPGA_RST_CTRL_OFFSET);
    xil_printf("\r SLCR FPGA RST CTRL REG: %x\n", status);
    status = XAxiDma_ReadReg(XPAR_AXI_DMA_0_BASEADDR, 0x00); // control status
    xil_printf("\r After resetting, AXI DMA MM2S CONTROL REG: %x\n", status);

 

 i put a delay after deassert the slcr.FPGA_RST_CTRL, and the output:

 Before resetting, AXI DMA MM2S CONTROL REG: 10002
 Before resetting, AXI DMA MM2S STATUS REG: 1
 SLCR FPGA RST CTRL REG: 1F33F00

the problem got stuck at when i try to access XAxiDma_ReadReg(*), and in ChipScope there's no reading action in s_axi_lite interface connected to AXI DMA.

 

And i then tried to use a project which only uses AXI DMA to transfer data, and i am sure that all the AXI DMA transactions finishes before i set the SLCR FPGA RST CTRL, and still afterwards i couldn't not access AXI DMA registers.

 

 

0 Kudos
Explorer
Explorer
5,885 Views
Registered: ‎11-21-2013

Re: After setting slcr.FPGA_RST_CTRL for PL, what is the sequence of starting the FPGA application?

Jump to solution
In the end, i used a GPIO to separated reset the user ip only, and i didn't reset the AXI interconnection, and it works!
0 Kudos