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Visitor jlaw
Visitor
142 Views
Registered: ‎02-04-2019

At what point are the M_AXI_HPM0_FPD signals set in the PS of the US+

For background, I am working on the ZCU102 Evaluation Board using Vivado 2018.2. The M_AXI_HPM0_FPD is connected to some 3rd party IP, but the crux of my problem happens when I am trying to read data out of a FIFO at a fixed address. 

When I run my software as Standalone OS application, I read some data like:

val = *physicalAddress

where physicalAddress is the address of the FIFO. As a standalone app, this trigers an AXI transaction with a burst of one, meaning I only read a single 32 bit data word.

When I run my software as VxWorks application (which uses virtual memory) I first establish a mmap between the physical memory of the 3rd party IP and virtual memory space then I read similarly to standalone:

val = *virtualAddress

However in this case the read of the FIFO iniates an AXI transaction with a burst of 4 words.

The data width of the M_AXI_HPM0_FPD is 128, where the data width of the IP is 32. I tried changing the width of the HPM0_FPD to 32, but that caused VxWorks to crash.

 

It is obvious to me that the change is occuring because of the Virtual Memory map and also there are differences in the way VxWorks initializes the harware components in the PS compared to how they are initialized in Standalone OS.

This question is not about VxWorks, I am trying to troubleshoot this issue and I am not sure where to look. My real question is what registers and components should I be looking at? I.E. which pieces of the PS have control over the AXI transactions on the M_AXI_HPM0_FPD. I know there is cache withen the APU, there is also and MMU being configured. There is also the CCI and FPD switch. Do I even have agency over these things? I notice there seem to not be any settings in Vivado for CCI, for example. I have looked at the ZCU102 TRM as well as arm documentation for the A53 and CCI. I know this is a broad question, but I am not finding the direction I need in the documentation. 

 

Thanks in advance for any help.

 

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Xilinx Employee
Xilinx Employee
71 Views
Registered: ‎01-09-2019

Re: At what point are the M_AXI_HPM0_FPD signals set in the PS of the US+

@jlaw 

Although you say this is not about VxWorks, I think the issue does potentially have to do a lot with VxWorks.  I particularly would look at that mmap as it seems that might not be properly setup to handle the conversion from physical to virtual.

You mentioned looking at UG1085, I just want to make sure you found the SMMU portion starting on page 76 and the ACE connecting to the CCI portion starting on page 1064.  You talked about configuring these components which can be done via software.  I would look at UG1137 for that (https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf) page 138.

Thanks,
Caleb
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