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Explorer
Explorer
624 Views
Registered: ‎01-13-2016

Automatic Pin Placement

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I have a zc706 board.

 

I would like to have a design where a Microblaze processor has access to the P3 RJ45 connector and can communicate with the J21 UART.

 

I made a design using the AXI 1G/2.5G Ethernet Subsystem block.  Now the existing ports on the design include gmii_rtl_15446, mdio_rtl_15446, uart_rtl_15446, and RST.RESET_RTL_15446.

 

I need to assign these to the hardware on the ZC706 board, but I don't understand how.

 

For an example, the MDIO port has INOUT pin mdio_rtl_mdio_io. I beleive this goes to pin C18 on the chip, which the schematic says is the PHI MDIO line. However, in my synthesized design when I try entering C18 in the Package Pin line  "C18 is an invalid placement site".

 

What is the proper way to assign pins? Or better  yet, is there a way to automatically have these RTL signals assigned to the correct locations?

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Voyager
Voyager
495 Views
Registered: ‎02-01-2013

Re: Automatic Pin Placement

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Oh, drat... Your follow-up question has me reading your original question differently now.

It now seems like you're trying to connect an AXI-based Ethernet MAC to MIO pins--ostensibly in order to use the Ethernet HW on the board that's connected to those pins.

Sorry; you can't do that.

You can export IO from PSU blocks (e.g., a GEM, including its MDC/MDIO) to the PL using EMIO and then connect those IO to the PCB using PL IO, but you can't go the other way. Meaning: you cannot use MIO pins as IO for PL logic.

You can connect your Microblaze to the PCB's Ethernet connector P3, but only by having that processor interact with a GEM inside the PSU--not by using any kind of PL-based Ethernet MAC. 

The AXI Enet IP you have added has no ability to communicated externally, unless you add an FMC module that provides a (GMII or RGMII) PHY and an RJ45 connector, and then connect that AXI IP to it.

-Joe G.

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4 Replies
Voyager
Voyager
557 Views
Registered: ‎02-01-2013

Re: Automatic Pin Placement

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PS pins are not assigned as PL pins are. There locations are fixed, so they need no location constraints.

If you notice in the ZC706 schematic, pin C18 is called PS_MIO53.  The Ethernet MDIO pins uses PS_MIO53 for EVERY Zynq chip.  PS_MIO53 differs in pin number (or ball location) from package to package, but the tool handles that re-mapping for you.

What you need to do is select the pin's specific functionality within the Vivado IP-Integrator PS Configurator.  This will result in the start-up software (FSBL) configuring the pin as you want it.

2018-12-18_11-06-34.jpg

-Joe G.

 

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Explorer
Explorer
503 Views
Registered: ‎01-13-2016

Re: Automatic Pin Placement

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So if I want to use the pin from the block diagram, I need to export it as an EMIO, but do I actually need to USE the pin from the ARM core, or can I connect a different IP and leave the EMIO pin unconnected?
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Voyager
Voyager
496 Views
Registered: ‎02-01-2013

Re: Automatic Pin Placement

Jump to solution

Oh, drat... Your follow-up question has me reading your original question differently now.

It now seems like you're trying to connect an AXI-based Ethernet MAC to MIO pins--ostensibly in order to use the Ethernet HW on the board that's connected to those pins.

Sorry; you can't do that.

You can export IO from PSU blocks (e.g., a GEM, including its MDC/MDIO) to the PL using EMIO and then connect those IO to the PCB using PL IO, but you can't go the other way. Meaning: you cannot use MIO pins as IO for PL logic.

You can connect your Microblaze to the PCB's Ethernet connector P3, but only by having that processor interact with a GEM inside the PSU--not by using any kind of PL-based Ethernet MAC. 

The AXI Enet IP you have added has no ability to communicated externally, unless you add an FMC module that provides a (GMII or RGMII) PHY and an RJ45 connector, and then connect that AXI IP to it.

-Joe G.

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Explorer
Explorer
486 Views
Registered: ‎01-13-2016

Re: Automatic Pin Placement

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Ok, so any of the ARM pins that go out to package pins are necessarily tied to the ARM and need to be used via PS in some way. Understood.

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