05-25-2016 12:58 AM
I have an issue to use Axi stream dma with SG multichannel mode. I used Vivado 15.4 and tested my design on zedboard.
I set up two rx channels for S2MM as shown in the block design figure.
My issue is that axi dma receives interleaved channel data from axi stream interconnect like the waveform figure.
From PG021, axi dma can't handle interleaved data at this granularity.
My question is how I can setup axi stream interconnect or axi stream fifo to interleave channel data at packet level.
06-07-2016 04:18 PM
06-08-2016 10:27 PM
Thank you for your reply.
In this test, I used the following options at AXI4-Stream Interconnect:
Enable ACLKEN : No
Use control register routing: No
Arbitrate on TLAST transfer : yes
Arbitrate on maximum number of transfers: 1
Arbitrate on number of LOW TVALID cycles : 0
Arbiter Algorithm : Round-Robin
Thus, I already set your suggestion on my configuration.
Do you have any other suggestions?
06-09-2016 07:56 AM
06-09-2016 11:48 PM
Here are S00_AXIS and S01_AXIS wave forms.
Two channel data are completely separated. axis_data_fifo_0 and axis_data_ffo_1 are allocated to channel 0 and channel 1, respectively.
I also set size of each fifo is much bigger than packet size (packet size is 0x100 and fifo depth is 0x4000). Still dma receives interleaved data.
I don't understand how axis interconnect handles axis stream data when two fifo have data to send out.
Thank you for your help.