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Adventurer
Adventurer
8,437 Views
Registered: ‎02-15-2016

Axi stream dma with SG multichannel mode issue

I have an issue to use Axi stream dma with SG multichannel mode. I used Vivado 15.4 and tested my design on zedboard.

 

I set up two  rx channels for S2MM as shown in the block design figure.  

My issue is that axi dma receives interleaved channel data from axi stream interconnect like the waveform figure.

From PG021, axi dma can't handle  interleaved data at this granularity.

My question is how  I can setup axi stream interconnect or axi stream fifo to interleave channel data at packet level.

 

Best regards,

 

 

axis_design.png
axis_multichannel.png
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4 Replies
Xilinx Employee
Xilinx Employee
7,914 Views
Registered: ‎08-02-2011

Re: Axi stream dma with SG multichannel mode issue

Hello,

If you set the AXIS interconnect to 'Arbitrate on tlast boundaries' it should fix it.
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Adventurer
Adventurer
7,856 Views
Registered: ‎02-15-2016

Re: Axi stream dma with SG multichannel mode issue

Thank you for your reply.

 

In this test, I used the following options at AXI4-Stream Interconnect:

 

Enable ACLKEN : No

Use control register routing: No

Arbitrate on TLAST transfer : yes

Arbitrate on maximum number of transfers: 1

Arbitrate on number of LOW TVALID cycles : 0

Arbiter Algorithm : Round-Robin

 

Thus, I already set your suggestion on my configuration.

Do you have any other suggestions?

 

Sincerely,

 

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Xilinx Employee
Xilinx Employee
7,834 Views
Registered: ‎08-02-2011

Re: Axi stream dma with SG multichannel mode issue

Ohh interesting. Is the data interleaved like that going into the interconnect? Can you post a screenshot of the slave sides of the interconnect?
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Adventurer
Adventurer
7,801 Views
Registered: ‎02-15-2016

Re: Axi stream dma with SG multichannel mode issue

Here are S00_AXIS and S01_AXIS wave forms. 

Two channel data are completely separated. axis_data_fifo_0 and axis_data_ffo_1 are allocated to channel 0 and channel 1, respectively.

 

I also set size of each fifo is much bigger than packet size (packet size is 0x100 and fifo depth is 0x4000). Still dma receives interleaved data.

I don't understand how axis interconnect handles axis stream data when two fifo have data to send out.

 

Thank you for your help.

 

 

 

 

 

channel_0_global.png
channel_1_global.png
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