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Scholar mrbietola
Scholar
2,569 Views
Registered: ‎05-31-2012

Axi to Vid locked problem

hi, i have this configuration

 

VDMA read -> OSD -> timing generator -> axi to vid

 

The VDMA transfers are started by a frame synch generated by the timing generator in the VBlank.

I want to control several DMAs, so i would use external frame synch.

This cause some problem of locking the video with the timing generator timings.

If i disable all OSD Layers, the video will lock, but if i enable 1 layer from DMA, the lock will goes down, the DMA and OSD are correctly setted, i think is a temporization problem. I don't know how can do it

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2 Replies
Xilinx Employee
Xilinx Employee
2,568 Views
Registered: ‎08-02-2011

Re: Axi to Vid locked problem

Are you following the recommendation from page 20-21 here:
http://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v3_0/pg044_v_axis_vid_out.pdf
www.xilinx.com
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Scholar mrbietola
Scholar
2,557 Views
Registered: ‎05-31-2012

Re: Axi to Vid locked problem

no, thanks for point me to this document (i have version 2.01a that doesn't contain that).

 

The problem in free run is that i need to reprogram my VDMA 2 times in a frame, how do i do that? with frame completition interrupt and frame counter?

 

The other problem i see is that when a read VDMA ends a frame, in free run it would start a new frame reading from a new buffer (or it repeat the same buffer if the new buffer is occupied by write) and it waits here for long. I don't want that latency between input and output increase because of that.

I think this free run mechanism would increase frame skip/repetition, since the read timing depends on how much data i will read

 

for example if original video is 1280x720      and i will output a   640x512 video in a 1280x720 frame, the VDMA timing output depends on the 640x512 image

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