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Scholar muravin
Scholar
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Registered: ‎11-21-2013

BMM file is not generated after migrating from 2015.2 to 2016.4

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Hello all,

 

As subject - this is a typical Microblaze project that used to be run in the past.The synthesis runs fine, the bitfile is generated, but there is no BMM file in the implementation folder. Therefore, we cannot compile the SDK into the Microblaze.

 

This is not the first time we are doing this, we normally do the VIVADO revision migration via a script and never had any issues at all.

 

When I open the implemented netlist, the LMB memory is there, and all RAMBxxE1 are marked with the proper BMM generation attribute.

 

Any ideas as to why this is happening?

 

Thank you

Vlad

Vladislav Muravin
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Scholar muravin
Scholar
7,973 Views
Registered: ‎11-21-2013

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hey Sebastian,

 

Thanks for this. Yes, I was able to also build yesteday a BSB-based design, and this one shows no issues. So I had migrated all our IPs to that design, and the new one does now have any issue, i.e. it can generate BMM/MMI.

 

I just wish Xilinx are reading this post and in the future make the messaging and error notifications more detailed.

 

Cheers

Vlad

Vladislav Muravin

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Adventurer
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Registered: ‎04-07-2014

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hi Vladislav,

 

since some Vivado Version, (I dont remember which), it creates .mmi files instead of .bmm.

 

The data2mem command seems to be an obsolete ISE command. It uses .bmm files. When called the blockram initialization takes a blink of an eye.

 

Now Vivado generates .mmi files and SDK uses updatemem. Here bram update is much slower. Therefore I use bmm + data2mem as long as it is supported or updatemem improves significantly.

 

We use the following flow which still works in Vivado 2016.4:

 

synthesize bd microblaze design out of context

call write_hwdef tcl command -> hwdef file is generated

synthesize and implement top level

call write_bmm tcl command -> bmm file is generated

call write_sysdef tcl command -> hdf file is generated

 

SDK uses hdf for hardware platform generation, detects bmm inside hdf and therefore uses data2mem instead of updatemem.

 

Hope that helps,

 

Yours,

Sebastian

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Scholar muravin
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Registered: ‎11-21-2013

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hi Sebastian,

 

Thanks for the prompt response. The MMI file is not generated either. We also do not synthesize BD OOC at this moment. Had issues in the past and gave up. HWDEF file is generated without issues.

 

Is there anything else I can try?

 

Oh btw, write_bmm gives me an error. The project apparetly does ont have those property to generated the BMM file. That's another new feature in 2016.4?

 

BR

Vlad

Vladislav Muravin
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Scholar muravin
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Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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If I open the implemented netlist, I get the following eror:

 

ERROR: [Memdata 28-96] Could not find a BMM_INFO_DESIGN property in the design. Could not generate the merged BMM file: ........
ERROR: [Common 17-69] Command failed: Failed to create a merged bmm file.

 

And that is despite the BRAMs allocated for the LMB are generated with the attribute

 

"DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B (RAMB36E1)"

Can someone please explain what is going on?

 

Thanks

Vlad

 

Vladislav Muravin
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Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hi Vladislav,

 

I checked with my Vivado 2016.4 by creating a BD containing microblaze. The BD is set to OOC automatically at my end (yellow square). However when i right click on the bd and choose "generate output products" the synthesis options are set to "out of context per IP". I assume, that the trouble starts there.

 

Can you try setting to "out of context per block design"? This corresponds to the tcl command

set_property synth_checkpoint_mode Singular [get_files blabla.bd]

I use the same command in my flow. which did the trick for me.

 

I have no idea, why my Vivado suggests the wrong ooc setup, perhaps another bug?

 

Regards,

Sebastian

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Scholar muravin
Scholar
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Registered: ‎11-21-2013

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Thanks for this Sebastian. Well, this has been our flow all along, i.e. we have a single BD with all IPs synthesized OOC within the single BD. Worked like magic since the first revision of VIVADO this flow has been enabled, i.e.

 

Furthermore, we had used the IP cache with checkpoint set to Hierarchical, i.e.

set_property synth_checkpoint_mode Hierarchical [het_files blabla.bd]

 

Xilinx: say something please.

 

BR

Vlad

 

 

Vladislav Muravin
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Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hi Vladislav,

 

does it work with option singular?

 

Is the synthesis time much longer now due to the lack of parallel synthesis?

 

Yours,

Sebastian

 

 

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Scholar muravin
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Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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The synthesis time is of course longer, and the results are the same, i.e. BMM is not written and I get that error. I think there is a synthesis/project settings that have been added/removed and since we have not been using MB based designs for about 4-5 VIVADO revisions. Well I hope someone will tell me what the hell is going on...

 

BR

Vlad

Vladislav Muravin
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Scholar muravin
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Registered: ‎11-21-2013

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Okay I did a little bit more digging. Xilinx, can you please suggest something?

 

No clue as to what's happening but I went back to 2015.2 project, opened the implementation, and I was able to execute:

 

write_bmm tt.bmm

/home/IGNIS/vmuravin/projects/orchestra/vivado/goku/goku11/tt.bmm

 

Furthermore, I queried get_property BMM_INFO_DESIGN [current_design ] and I got this (note that 2016.4 returns nothing on that query):


<?xml version="1.0" encoding="UTF-8"?> <AddressMap Version="1" Minor="0" ProcessorElementCount="1"> <Processor Name="system_i_mb_mba" Type="MICROBLAZE-LE" Id="100" Instance="system_i/mb_mba" SpaceElementCount="1"> <AddressSpace Name="system_i_system_microblaze_memory_inst_ilmb_bram_if_mba" Style="byte" StartAddress="0x00000000" EndAddress="0x0003FFFF" Instance="system_i/system_microblaze_memory/inst_ilmb_bram_if_mba" RangeElementCount="1"> <Range Type="RAMB32" BusBlockElementCount="2"> <Block DeviceElementCount="32"> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[31].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="31:31"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[30].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="30:30"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[29].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="29:29"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[28].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="28:28"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[27].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="27:27"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[26].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="26:26"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[25].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="25:25"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[24].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="24:24"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[23].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="23:23"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[22].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="22:22"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[21].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="21:21"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[20].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="20:20"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[19].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="19:19"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[18].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="18:18"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[17].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="17:17"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[16].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="16:16"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="15:15"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="14:14"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="13:13"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="12:12"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="11:11"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="10:10"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="9:9"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="8:8"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="7:7"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="6:6"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="5:5"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="4:4"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="3:3"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="2:2"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="1:1"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B" Type="RAMB32" Width="0:0"> </Device> </Block> <Block DeviceElementCount="32"> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[31].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="31:31" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[30].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="30:30" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[29].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="29:29" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[28].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="28:28" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[27].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="27:27" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[26].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="26:26" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[25].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="25:25" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[24].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="24:24" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[23].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="23:23" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[22].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="22:22" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[21].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="21:21" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[20].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="20:20" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[19].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="19:19" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[18].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="18:18" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[17].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="17:17" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[16].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="16:16" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="15:15" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="14:14" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="13:13" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="12:12" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="11:11" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="10:10" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="9:9" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="8:8" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="7:7" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="6:6" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="5:5" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="4:4" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="3:3" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="2:2" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="1:1" Depth="32768:65535"> </Device> <Device Instance="system_i/system_microblaze_memory/inst_lmb_bram_mba/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_T" Type="RAMB32" Width="0:0" Depth="32768:65535"> </Device> </Block> </Range> </AddressSpace> </Processor> </AddressMap>

Vladislav Muravin
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Adventurer
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Registered: ‎04-07-2014

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hi Vlad,

 

I tried the following tcl script in Vivado 2016.4 and SDK export (using MMI) worked. BMM file is also generated. Perhaps you can find the difference to your design flow?

 

create_project vlad_test C:/vlad_test -part xc7k325tffg900-2
set_property board_part xilinx.com:kc705:part0:1.4 [current_project]
set_property target_language VHDL [current_project]
create_bd_design "design_1"
create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config {local_mem "8KB" ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0" clk "New Clocking Wizard (100 MHz)" }  [get_bd_cells microblaze_0]
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "sys_diff_clock ( System differential clock ) " }  [get_bd_intf_pins clk_wiz_1/CLK_IN1_D]
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "reset ( FPGA Reset ) " }  [get_bd_pins clk_wiz_1/reset]
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "reset ( FPGA Reset ) " }  [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/microblaze_0 (Periph)" Clk "Auto" }  [get_bd_intf_pins axi_gpio_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "led_8bits ( LED ) " }  [get_bd_intf_pins axi_gpio_0/GPIO]
save_bd_design
close_bd_design [get_bd_designs design_1]
make_wrapper -files [get_files C:/vlad_test/vlad_test.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse C:/vlad_test/vlad_test.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
launch_runs impl_1 -to_step write_bitstream -jobs 6

Regards,

Sebastian

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Scholar muravin
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Registered: ‎11-21-2013

Re: BMM file is not generated after migrating from 2015.2 to 2016.4

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Hey Sebastian,

 

Thanks for this. Yes, I was able to also build yesteday a BSB-based design, and this one shows no issues. So I had migrated all our IPs to that design, and the new one does now have any issue, i.e. it can generate BMM/MMI.

 

I just wish Xilinx are reading this post and in the future make the messaging and error notifications more detailed.

 

Cheers

Vlad

Vladislav Muravin

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