HERE IS THE CODE; module bram_pl( input clk, input rst, input [31:0]din, input [3:0]wr_addr, input we, output wire[31:0]dout ); /////////////////////////////////////////////////////////////////////////////////// reg[31:0]ram[15:0]; reg [31:0]dout_sig = 32'd0; reg [3:0]rd_Addr = 4'b0000; reg [3:0]wr_addr_sig = 4'b0000; reg [2:0]state = 3'b000; reg [31:0]din_sig = 32'd0; /////////////////////////////////////////////////////////////////////////////////// parameter INIT_STATE = 3'b000; parameter RAM_OPERATION = 3'b001; parameter READ_TRIGGER_START = 3'b010; parameter ADDR_INC = 3'b011; parameter WB = 3'b100; parameter OUTPUT_STATE_TRIGGER_STOP = 3'b101; parameter DONE_STATE = 3'b110; /////////////////////////////////////////////////////////////////////////////////// assign dout = dout_sig; assign wr_addr = wr_addr_sig; assign din = din_sig; //////////////////////////////////////////////////////////////////////////////////// always@(posedge clk) begin case(state) INIT_STATE: if(!rst) state <= RAM_OPERATION; else state <= INIT_STATE; RAM_OPERATION: begin if(we == 1) ram[wr_addr_sig] <= din_sig;//data given to Ram,which increments Address(ie;Write Address) else begin rd_Addr <= wr_addr_sig;//rd_Addr given to Read data state <= READ_TRIGGER_START;////BRAM operation end end READ_TRIGGER_START: begin dout_sig <= ram[rd_Addr];//1.)Read data at each and every address state <= ADDR_INC; end ADDR_INC: begin din_sig <= din_sig + 32'd1; wr_addr_sig <= wr_addr_sig + 4'd1;//2.)Add 1 to it state <= WB; end WB: begin ram[wr_addr_sig] <= din_sig;//WRITE BACK state <= OUTPUT_STATE_TRIGGER_STOP; end OUTPUT_STATE_TRIGGER_STOP: begin dout_sig <= ram[wr_addr_sig];///writing of data to output signal state <= DONE_STATE; end DONE_STATE: begin dout_sig <= 32'd0; state <= DONE_STATE; end default: begin dout_sig <= 32'd0; din_sig <= 32'd0; end endcase end endmodule TESTBENCH TOO; module TB_BRAM(); reg clk; reg [31:0]din; reg [3:0]wr_addr; reg rst; reg we; wire[31:0]dout; bram_pl b1 (.clk(clk),.din(din),.wr_addr(wr_addr),.rst(rst),.we(we),.dout(dout)); initial begin clk = 1'b0; din = 32'd0; we = 1'b0; wr_addr = 4'd0; end always #5 clk = ~clk; initial begin rst = 1'b1; #10; rst = 1'b0; //#70; //rst = 1'b1; //#75; //rst = 1'b0; end initial begin din = 32'h0a3d70a3;//100mhz wr_addr = 4'd0; #100; din = 32'h0e560418;//140mhz wr_addr = 4'd1; we = 1'b1; #100; din = 32'h147ae147;//200mhz wr_addr = 4'd2; we = 1'b1; #100; din = 32'h20c49a5;//320mhz wr_addr = 4'd3; we = 1'b1; #100; wr_addr = 4'd0; we = 1'b0; #100; wr_addr = 4'd1; we = 1'b0; #100; wr_addr = 4'd2; we = 1'b0; #100; wr_addr = 4'd3; we = 1'b0; #100; end endmodule
@ronnywebers wrote:@sam007, I don't have any code ready at this moment, especially not Verilog as I use VHDL
Did you try to write to the BRAM from the PS and read back from the PS first? Just to see that the PS code is working fine.
Also can you share a screenshot of your entire block diagram here and your entire verilog file? (please use the 'insert code' function for this, it's the </> icon above this editor.
Did you add an 'ILA' on the interfaces to see what's happening?
1.)sir..since Iam using Verilog ...not SYSTEM verilog..so i think..ENUM is something iam not too familiar using
2.)secondly i have mentioned the internal signals,"current state"...here i have changed the code..and look into the simulation as my DATA_IN_SIG and DATA_OUT_SIG are showing unknown.
3.)i havent used ILA since...my normal simulation isnt coming as expected...please help me in framing that logic,
and tell me what i need to do,in order to correct that...I have shared my code.....
4.) I havent packaged it...since iam checking functionlity....
5.)i have attached the simulation shots and the DUT and testbench...
6.) Here since you discussed about this logic"you could for example build an FSM that reads the data on each address, adds 1 to it, and writes it back. Then you'll also need something to trigger a 'start' of this caluclation, and optinally signal an end."..i have written that code itself...and there is one code in VHDL which they tried the same logic...please guide me on how to use it...iam attaching that to...
THANKS IN ADVANCE
//DUT// module bram_pl( input clk, input Rst, input[31:0]data_in, input[31:0]address, input wr_enable, output wire[31:0] data_out ); /////////////////////////////////////////////////////////////////////////////////////////////// reg [31:0]data_out_sig = 32'h00000000; reg [31:0]data_in_sig = 32'h00000000; reg [2:0]current_state = 3'b000; reg [31:0]address_wr_sig = 32'h00000000; reg [31:0]RAM[1023:0]; reg [31:0]address_rd_sig = 32'h00000000; /////////////////////////////////////////////////////////////////////////////////////////////// parameter INIT = 3'b000; parameter READING_ADDRESS = 3'b001; parameter INC_ADDRESS = 3'b010; parameter WRITE_BACK = 3'b011; parameter DONE = 3'b100; /////////////////////////////////////////////////////////////////////////////////////////////// assign data_out = data_out_sig; assign data_in = data_in_sig; assign address = address_rd_sig; /////////////////////////////////////////////////////////////////////////////////////////////// always@(posedge clk) begin case(current_state) INIT: if(Rst == 1) begin current_state <= INIT; data_out_sig <= 32'h00000000; end else current_state <= READING_ADDRESS; READING_ADDRESS: begin RAM[address_rd_sig] <= data_in_sig; data_out_sig <= RAM[address_rd_sig]; current_state <= INC_ADDRESS; end INC_ADDRESS: begin data_in_sig <= data_in_sig + 32'h04000004; address_rd_sig <= address_rd_sig + 32'h00000004; current_state <= WRITE_BACK; end WRITE_BACK: if(wr_enable == 1) RAM[address_rd_sig] <= data_in_sig; else begin address_wr_sig <= address_rd_sig; current_state <= DONE; end DONE: begin data_out_sig <= RAM[address_wr_sig]; current_state <= DONE; end default: begin data_out_sig <= 32'h00000000; address_rd_sig <= 32'h00000000; end endcase end endmodule //TB// module TB_BRAM(); reg clk; reg [31:0]data_in; reg [31:0]address; reg wr_enable; reg Rst; wire[31:0]data_out; bram_pl b1 (.clk(clk),.data_in(data_in),.address(address),.Rst(Rst),.wr_enable(wr_enable),.data_out(data_out)); initial begin clk = 1'b0; end always #5 clk = ~clk; initial begin Rst = 1'b1; #10; Rst = 1'b0; //#70; //rst = 1'b1; //#75; //rst = 1'b0; end initial begin wr_enable = 1'b1; #35; wr_enable = 1'b0; #50; wr_enable = 1'b1; #75; wr_enable = 1'b0; #105; end endmodule
@sam007, I'd try to find a verilog tutorial that first gives you a working module and testbench, so you can start from that. I googled a bit and found the one attached. I really think you should calm down and have a look at that tutorial first. you'll win back that time later.
Looking at that code quickly, I think at least one issue is here :
I think you should end your init state here. If you do so, you'll need to remove one 'end' statement at the bottom of your code.
Then next, your testbench looks incomplete - you should define signals for all inputs (stimuli) of your DUT, these are :
input clk, input Rst, input[31:0]data_in, input[31:0]address, input wr_enable,
If I'm correct, you're not defining anything for data_in and address, hence the red signals ..
Also, look at your simulation : next_state shows that immediately after reset ends, you go from 0 -> 1 -> 2 -> 3 -> 4, and you seem to stay in '4' forever ... ? So there's one of your issues I guess, but to be honest, your design looks unclear to me ...
try to draw your system on paper : start drawing an FSM block and a BRAM block, and see how these connect. Then create 2 verilog source files, one for the BRAM, one for the FSM, then hook both up in a testbench. I'm confused by your files : you also showed a screenshot of 'counter_data.vhd' which is a VHDL file... I don't see how / where that is connected to your FSM or BRAM ...?
Also, check UG937 - Logic Simulation Tutorial - it might take you a few hours to go through this, but you'll have a good verilog code and testbench example.
I really recommend you reading a good Verilog book that approaches things in a modular way, you'll win all that time back. A good book IMHO is from Pong P. Chu, it's rather old, but still a good one to start with. He has many other good books.
i have done changes,here it goes
1.) I have added that "end" in the INIT state,and thus there is a more Systematic flow to the FSM.
2.)i have defined the "Data_in" and "Address values" in the Testbench. I have a Question... is it Required to define these values in the DUT.(ie;0a3d70a3,values so on...) TESTBENCH ATTACHED TOO.
3.) In the simulation it is not getting stuck at that "4" state...but atleast DATA_IN and DATA_OUT are kindof Matching..where DATA_IN is being incremented,and DATA_OUT Increment occurs..(SIMULATION SNAPSHOT ATTACHED)
4.) I Have attached a changed version of this code.(DUT AND TESTBENCH).So i want to understand one thing...BRAM is just basic READ/WRITE..right? or is there something else more to be added within the bram.
Secondly,this statement in the DUT
data_in_sig <= data_in_sig + 32'h04000004;
address_rd_sig <= address_rd_sig + 4'd4;
is the logic of the FSM that you mentioned ..quoted by Yourself" FSM that reads the data on each address, adds 1 to it, and writes it back." is this that logic....
here i have Written "BRAM and the Logic which you mentioned in one FSM"..is it the right thing what iam doing?
or should i just write one source for Conventional BRAM and one FSM...for the logic that is mentioned.. by you.
separtely
5.) you said to make two files one for FSM and one for BRAM them separtely,is doing them together an issue...please let me know on this..........
6.)iam going through Your references of FSM pdf which you sent,Verilog book,and logic simulation...i now what path i have to follow...it will take time..but good in long term.
7.)finally can you refer me a good soure for basic digital logic....for LOGIC SYNTHESIS...and hardware analysis?
let me know on the fsm and bram..confusion i have
THANKS YOU ADVANCE
//DUT// module bram_pl( input clk, input Rst, input[31:0]data_in, input[3:0]address, input wr_enable, output wire[31:0] data_out ); /////////////////////////////////////////////////////////////////////////////////////////////// reg [31:0]data_out_sig = 32'h00000000; reg [31:0]data_in_sig = 32'h00000000; reg [2:0]current_state = 3'b000; reg [3:0]address_wr_sig = 4'd0; reg [31:0]RAM[15:0]; reg [3:0]address_rd_sig = 4'd0; /////////////////////////////////////////////////////////////////////////////////////////////// parameter INIT = 3'b000; parameter READING_ADDRESS = 3'b001; parameter INC_ADDRESS = 3'b010; parameter WRITE_BACK = 3'b011; parameter DONE = 3'b100; /////////////////////////////////////////////////////////////////////////////////////////////// assign data_out = data_out_sig; //assign data_in = data_in_sig; //assign address = address_rd_sig; /////////////////////////////////////////////////////////////////////////////////////////////// always@(posedge clk) begin data_in_sig <= data_in; address_rd_sig <= address; case(current_state) INIT: begin if(Rst == 1) begin current_state <= INIT; data_out_sig <= 32'h00000000; end else current_state <= READING_ADDRESS; end///end has been added....to end the "INIT" state ..as the FSM will be stuck in the same state. READING_ADDRESS: begin RAM[address_rd_sig] <= data_in_sig; data_out_sig <= RAM[address_rd_sig]; current_state <= INC_ADDRESS; end INC_ADDRESS: begin data_in_sig <= data_in_sig + 32'h04000004; address_rd_sig <= address_rd_sig + 4'd4; current_state <= WRITE_BACK; end WRITE_BACK: if(wr_enable == 1) begin RAM[address_rd_sig] <= data_in_sig; current_state <= DONE; end else begin address_wr_sig <= address_rd_sig; current_state <= DONE; end DONE: begin data_out_sig <= RAM[address_wr_sig]; current_state <= INIT;/////////Had Written "DONE"but in simulation,FSM was stuck..so its going back to 1(READING_ADDRESS) end default: begin data_out_sig <= 32'h00000000; address_rd_sig <= 4'd0; end endcase end endmodule //TB// module TB_BRAM(); reg clk; reg [31:0]data_in; reg [3:0]address; reg wr_enable; reg Rst; wire[31:0]data_out; bram_pl b1 (.clk(clk),.data_in(data_in),.address(address),.Rst(Rst),.wr_enable(wr_enable),.data_out(data_out)); initial begin clk = 1'b0; end always #5 clk = ~clk; initial begin Rst = 1'b1; #10; Rst = 1'b0; //#70; //rst = 1'b1; //#75; //rst = 1'b0; end initial begin data_in = 32'h0a3d70a3; address = 4'd0; wr_enable = 1'b1; #100; data_in = 32'h0e560418; address = 4'd1; wr_enable = 1'b1; #100; data_in = 32'h147ae147; address = 4'd2; wr_enable = 1'b1; #100; data_in = 32'h20c49ba5; address = 4'd3; wr_enable = 1'b1; #100; address = 4'd0; wr_enable = 1'b0; #100; address = 4'd1; wr_enable = 1'b0; #100; address = 4'd2; wr_enable = 1'b0; #100; address = 4'd3; wr_enable = 1'b0; #100; end endmodule
sir there is increment in data_out values because of the "data_in <= data_in + 32'h04000004"
THANKS IN ADVANCE
here the simulation...iam not sure whats going ...its incremneted the dout + 4 ...from the input data...just verify this
THANKS IN ADVANCE,@ronnywebers