I have a question please need some help with this!!!....I have an SPI Module...in which i use to Run via FPGA Switches...First switch 1 would have loaded an inital frequency of 100mhz... and switch 2 would commence Frequency Hopping..from 100 mhz to 140mhz to 200 mhz to 330mhz...and then when in switch 3 it would go back to init 100mhz frequency again......
Now the spec given to me is as follows use a 32 bit internal register instead of these "SWITCHES" .......and when this 32 bit register....the Bit[0] -> 0(Falling Edge),the it should perform the operation of Switch 1
Next the 32 bit register..when Bit[1] -> 1(Rising Edge) then it should perform the Switch 2 operation ie; Frequency Hopping...
next the 32 bit Register ..when bit[2] -> 0 (Falling Edge),then it should perform the switch 3 operation..that is init DDS...same as switch 1
Here instead of using Switches...the PS will write the values to Port A(PS) and Port B(PL) will read those values
I TRIED TO USE reg[0] == 0
{Edge_det_sig[0]} == 1'b0,{Edge_det_sig[1]} == 1'b1..in PL..design...no effect..what should i do...for this kind of spec? i have attached the code please..
module Spi_Mod(
input wire sysclk,
output wire sclk,
output wire sig1ms_sig,
output wire cs,
output wire[3:0]functional_pins,
output wire master_reset,
output wire io_update,
output wire [2:0]ps,
output wire[31:0] Edge_det,
output mosi
);
//////////////////////////////////////////////////////////////////////////////////////
parameter [2:0]idle_state = 3'b000;
parameter [2:0]master_reset_state = 3'b001;
parameter [2:0]wait_state = 3'b010;
parameter [2:0]data_state = 3'b011;
parameter [2:0]repeat_state = 3'b100;
parameter [2:0]update_state = 3'b101;
parameter [2:0]stop_state = 3'b110;
/////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
reg sclk_reg = 1'b0;
reg cs_reg = 1'b1;
reg [3:0]func_pins = 4'b0001;
reg master_reset_reg = 1'b0;
reg io_update_reg = 1'b0;
reg [2:0]ps_reg = 3'b000;
reg mosi_reg = 1'b0;
reg [2:0]state = 3'b000;
reg [2:0]update_cntr = 3'b000;
reg [39:0]data = 40'd0;
reg [5:0]cnt = 6'd0;
reg [2:0]freq_cnt = 3'b000;
reg [39:0]freq_ch = 40'd0;
reg sig1ms = 1'b0;
reg [31:0]Edge_det_sig = 32'h00000000;///for edge detect Ps logic.
reg [31:0]cnt_1ms = 32'd0;
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////
assign sclk = sclk_reg;
assign cs = cs_reg;
assign functional_pins = func_pins;
assign master_reset = master_reset_reg;
assign io_update = io_update_reg;
assign ps = ps_reg;
assign sig1ms_sig = sig1ms;
assign Edge_det = Edge_det_sig;
assign mosi = mosi_reg;
////////////////////////////////////////// //////////////////////////////////////////////////
always @(posedge sysclk)
begin
if(cnt_1ms == 32'd100000)//1ms logic
begin
cnt_1ms <= 0;
sig1ms <= 1;
end
else
begin
cnt_1ms <= cnt_1ms + 1;
sig1ms <= 0;
end
case(state)
idle_state:
begin
if({Edge_det_sig[0]} == 1'b0)
begin
state <= master_reset_state;
data <= {8'h00,32'h0001010a};
end
else if({Edge_det_sig[0]} == 1'b1)
begin
func_pins <= 4'b0001;//Serial_state
io_update_reg <= 1'b0;
master_reset_reg <= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b1;
state <= idle_state;
end
end
master_reset_state:
begin
func_pins <= 4'b0001;//Serial_state
io_update_reg <= 1'b0;
master_reset_reg <= 1'b1;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b1;
state <= wait_state;
end
wait_state:
begin
func_pins <= 4'b0001;
io_update_reg <= 1'b0;
master_reset_reg <= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b0;
state <= data_state;
end
data_state:
begin
func_pins <= 4'b0001;
io_update_reg <= 1'b0;
master_reset_reg <= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b0;
mosi_reg <= {data[39]};//msb sent 1st to MOSI output.
state <= repeat_state;
end
repeat_state:
begin
func_pins <= 4'b0001;
io_update_reg <= 1'b0;
master_reset_reg <= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b1;
cs_reg <= 1'b0;
data <= {data[38:0],1'b0};
if(cnt > 6'd38)
state <= update_state;
else
begin
cnt <= cnt + 1;
state <= data_state;
end
end
update_state:
begin
func_pins <= 4'b0001;
ps_reg <= 3'b000;
cs_reg <= 1'b0;
master_reset_reg<= 1'b0;
io_update_reg <= 1'b1;
sclk_reg <= 1'b0;
cnt <= 6'd0;
update_cntr <= update_cntr + 1;
data <= freq_ch;
if(update_cntr == 3'b000)
begin
data <= {8'h03,32'h01052120};
state <= wait_state;
end
if(update_cntr == 3'b001)
begin
data <= {8'h03,32'h00052120};
state <= wait_state;
end
else if(update_cntr == 3'b010)
begin
data <= {8'h01,32'h00800900};
state <= wait_state;
end
else if(update_cntr == 3'b011)
begin
data <= {8'h0c,32'h0fd70000};
state <= wait_state;
end
else if(update_cntr == 3'b100)
begin
data <= {8'h0b,32'h0a3d70a3};//amplitude with init freq,ie 100mhz
state <= wait_state;
update_cntr <= 3'b110;
end
else if(update_cntr == 3'b101)
begin
io_update_reg <= 1'b0;
data <= freq_ch;
state <= wait_state;
end
else if(update_cntr == 3'b110)
begin
mosi_reg <= 1'b0;
state <= stop_state;
end
end
stop_state:
begin
state <= stop_state;
update_cntr <= 3'b000;
io_update_reg <= 1'b0;
master_reset_reg <= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b1;
mosi_reg <= 1'b0;
func_pins <= 4'b0001;//serial_state
if({Edge_det_sig[0]} == 1'b0)
begin
state <= master_reset_state;
data <= {8'h00,32'h0001010a};//amplitude phase
update_cntr <= 3'b100;
end
else if({Edge_det_sig[0]} == 1'b0)
begin
freq_ch <= 40'h0;
state <= stop_state;
end
if({Edge_det_sig[1]} == 1'b1 )
begin
if(sig1ms == 1)
begin
freq_cnt <= freq_cnt + 1;
if(freq_cnt == 3'b000)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h0e560418};// 140 mhz
state <= update_state;
end
if(freq_cnt == 3'b001)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h147ae147}; //200 mhz
state <= update_state;
end
if(freq_cnt == 3'b010)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h20c49ba5};//320 mhz
state <= update_state;
end
if(freq_cnt == 3'b011)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h2219652b};//333 mhz
state <= update_state;
freq_cnt <= 3'b000;
end
else if({Edge_det_sig[1]} == 1'b0)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h0e560418};// init freq in hopping that is 140 mhz
state <= update_state;
freq_cnt <= 3'b000;
end
end
end
if({Edge_det_sig[0]} == 1'b0)
begin
update_cntr <= 3'b101;
freq_ch <= {8'h0b,32'h0e560418};
state <= update_state;
freq_cnt <= 3'b000;
end
else if({Edge_det_sig[0]} == 1'b1)
begin
update_cntr <= 3'b101;
freq_ch <= 40'h0;//140mhz
state <= update_state;
end
end
default:
begin
io_update_reg <= 1'b0;
master_reset_reg<= 1'b0;
ps_reg <= 3'b000;
sclk_reg <= 1'b0;
cs_reg <= 1'b1;
func_pins <= 4'b0001;//serial_state
end
endcase
end
endmoduleTHANKS @ronnywebers
