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Visitor javierperez
Visitor
1,407 Views
Registered: ‎07-30-2017

Bare-Metal System Running on Both Cortex-A9 Processors

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Hi, i have a full functional dual core Bare.metal project using jtag, now i want to programm the flash with the same project so y create FSBL file on cpu0 and create the image adding all .elf for each core and a microblaze. Then i program the qspi flash and only the cpu0 works. I find  XAPP1079  talking about changing the FSBL then i find how in  'AR# 51956 Zynq-7000 Example Design - Modify the 14.2 FSBL to load multiple executable partitions' but im useing the new vivado and sdk software an they claim me to change the ' image_mover.c' with i´ve got but i cant find the secction 'update_status_reg:' where the new functions must be inserted. Any helps? Thanks.

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1 Solution

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1,918 Views
Registered: ‎11-07-2017

Re: Bare-Metal System Running on Both Cortex-A9 Processors

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I have developed a similar project using Vivado 2017.1 and SDK 2017.1.

If you use recent SDK (example 2017.x) you don't have to modify FSBL. It automatically loads

multiple source/bitmap from bin file.

To start core#1 from core#0 use the following instruction:

 

#define sev() __asm__("sev")
#define CPU1STARTADR 0xfffffff0

void startSecondCore(void)
{
  Xil_Out32(CPU1STARTADR, 0x00200000); // 0x200000 is my base code area for CORE#1
  dmb(); //waits until write has finished
  Xil_DCacheFlushLine(CPU1STARTADR);
  sev();
}

On my application this work fine.

 

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2 Replies
1,919 Views
Registered: ‎11-07-2017

Re: Bare-Metal System Running on Both Cortex-A9 Processors

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I have developed a similar project using Vivado 2017.1 and SDK 2017.1.

If you use recent SDK (example 2017.x) you don't have to modify FSBL. It automatically loads

multiple source/bitmap from bin file.

To start core#1 from core#0 use the following instruction:

 

#define sev() __asm__("sev")
#define CPU1STARTADR 0xfffffff0

void startSecondCore(void)
{
  Xil_Out32(CPU1STARTADR, 0x00200000); // 0x200000 is my base code area for CORE#1
  dmb(); //waits until write has finished
  Xil_DCacheFlushLine(CPU1STARTADR);
  sev();
}

On my application this work fine.

 

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Visitor javierperez
Visitor
1,282 Views
Registered: ‎07-30-2017

Re: Bare-Metal System Running on Both Cortex-A9 Processors

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Xil_DCacheFlushLine(CPU1STARTADR); its really the key in order two work i find differents solutions but this is the one thath include it and works perfect thanks for your support
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