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Registered: ‎05-30-2018

Basic SMMU Questions with Custom IP


I am currently working on an AXI Master that reads Data from the PS through HP1 and it should get the start-address of the data through an AXI Light Slave interface.

I would like to use the SMMU for my AXI Master and for this I read the following guides:

Zynq UltraScale MPSOC SMMU

Xen and PL Masters


Both of them were using DMA or CDMA and I am stuck at the point where I should set the Stream IDs.

Do I have to write a Device Driver and create an entry in the Device Tree? I am new to the device tree, so my question may seem pretty stupid.

My AXI Master only needs to read Data from the PS and for this modifying the device tree seems overkill. I only want my Master to be able to pass through the SMMU and set the StreamIDs without too much work.

I would really like to use the SMMU for this though. Alternativly I would use a kernel space driver to allocate memory with the same virtual and physical address.


Thanks for any help!

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3 Replies
Registered: ‎04-19-2018

Re: Basic SMMU Questions with Custom IP

If the data you want to read is serial (not MM) then I'd say all you need is a DMA (not CDMA). your DMA will be mapped somewhere in your memory and that's all you need I bet. Why virtualizing memory?
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Registered: ‎05-30-2018

Re: Basic SMMU Questions with Custom IP

No, the data is in the PS and needs to read from PL over a direct Master.

Like my name indicates this is not a "real-world project"

and using the SMMU would be a nice "educational extra". In a later project, I would have "real" use for virtualization.


But for now, while it is not time-sensitive, I would like to know what has to be done to get the SMMU up and running without the needing to edit the device tree. Or a link to a tutorial on how to create one for the SMMU.


I don't want to use a DMA IP-Core, I would like to use my own.

I assume this seems pretty weird for somehow that knows how to do it, but I would like to know how mainly for educational purposes.



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Registered: ‎05-30-2018

Re: Basic SMMU Questions with Custom IP

Ok, so I have done the following:


I changed my AXI Master from reading to writing and switched from HP to HPC0.


I created a simple entry in "system-user.dtsi" which looks like this:


/include/ "system-conf.dtsi"
/ {
		iommus = <&smmu 0x200>;

&smmu {
   status = "okay";

And zynq_benchmark is the name of my IP Core which is connected through the HPC0 Port with a constant WID of 0 (this is responsible for the 0x200 encoding).


I set axiwprot to  0x2 like it is mentioned in the SMMU Xen Tutorial and set the Cache signals to 0xb.


I used System-ILA to verify that the data that is written to HPC0 is correct; the "Virtual Address" and the Data is correct. The Write Transaction is valid and my AXI Master does his job.

But if I read the Array I created in my program with calloc (this is the virtual address I sent to my master), nothing changes, even though the data from my write transaction is always different to 0.


So I thought that if I use PetaLinux the SMMU gets configured if I enable it in the device tree through the FSBL (which is integrated in BOOT.BIN). During boot up these messages indicate that everything is beeing configured:


[    0.210449] arm-smmu fd800000.smmu: SMMUv2 with:
[    0.210461] arm-smmu fd800000.smmu:  stage 1 translation
[    0.210474] arm-smmu fd800000.smmu:  stage 2 translation
[    0.210486] arm-smmu fd800000.smmu:  nested translation
[    0.210502] arm-smmu fd800000.smmu:  stream matching with 48 register groups, mask 0x7fff
[    0.210528] arm-smmu fd800000.smmu:  16 context banks (0 stage-2 only)
[    0.210545] arm-smmu fd800000.smmu:  Supported page sizes: 0x61311000
[    0.210558] arm-smmu fd800000.smmu:  Stage-1: 48-bit VA -> 48-bit IPA
[    0.210572] arm-smmu fd800000.smmu:  Stage-2: 48-bit IPA -> 48-bit PA
[    0.210777] vdso: 2 pages (1 code @ ffffff8008967000, 1 data @ ffffff8008cb4000)
[    0.210801] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.211268] DMA: preallocated 256 KiB pool for atomic allocations
[    0.221279] reset_zynqmp reset-controller: Xilinx zynqmp reset driver probed
[    0.222129] ARM CCI_400_r1 PMU driver probed
[    0.222290] iommu: Adding device fd500000.dma to group 0
[    0.222453] iommu: Adding device fd510000.dma to group 1
[    0.222601] iommu: Adding device fd520000.dma to group 2
[    0.222750] iommu: Adding device fd530000.dma to group 3
[    0.222898] iommu: Adding device fd540000.dma to group 4
[    0.223053] iommu: Adding device fd550000.dma to group 5
[    0.223200] iommu: Adding device fd560000.dma to group 6
[    0.223350] iommu: Adding device fd570000.dma to group 7
[    0.224526] iommu: Adding device ff0e0000.ethernet to group 8
[    0.225316] iommu: Adding device ff0f0000.spi to group 9
[    0.225748] iommu: Adding device fd0c0000.ahci to group 10
[    0.225902] iommu: Adding device ff170000.sdhci to group 11


So I think that the SMMU doesn't allow my transaction but I don't know what else needs to be configured.

I would be very grateful if somebody could help me and tell me how they got the SMMU with a custom IP Core running.

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