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Adventurer
Adventurer
3,282 Views
Registered: ‎09-08-2016

Block design-----Create Inteface Port mode selection

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Hi Expert,

    I'm doing a project which need to make AXI connection out of the block design,so I used Create Interface Port option to create it.

 

The following picture's M00_AXI is the bus which need to make connection out of the block design:

Image 2.png

 

The following is the question: MASTER or SLAVE should to select of the mode????

 

Image 1.png

 

Best Regard!

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1 Solution

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Adventurer
Adventurer
5,147 Views
Registered: ‎09-08-2016

Re: Block design-----Create Inteface Port mode selection

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    Yes, you're right.Actually I want to control one module which interface is AXI Lite using JTAG outside of the block design. So firstly I add an instance of this module in the block design and it work normally. But when I add this slave module out side of the block design, the IDL will not work. Finally I found that the AXI slave module's interface is AXI Lite, but the AXI interconnect's interface is AXI4. when you connect the two module inside of the block design, the system will add an AXI protocol convertor between the two module automatically, But if you connect M00_AXI outside of the block design, the system will not add an AXI protocol convertor automatically. So when I add an AXI protocol convertor manually it will work noramally.

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5 Replies
Explorer
Explorer
3,268 Views
Registered: ‎04-12-2017

Re: Block design-----Create Inteface Port mode selection

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You don't show all the design so I am guessing a bit.

 

I guess there is a processor as a master of the AXI interconnect on the left side. The interconnect connects to two slaves, one of those is outside the FPGA. Since the device connected outside the FPGA is a slave, the port itself is a MASTER.

Avi Chami MSc
FPGA Site
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Moderator
Moderator
3,192 Views
Registered: ‎11-09-2015

Re: Block design-----Create Inteface Port mode selection

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Hi @alex_sun,

 

When you create an external port, just use Create Interface Port and it should be already configured properly (at least for an output).

 

For information: if this is an output this is a Master, if it is an input, it is a slave. So in your case, it should be a Master (as this is an output of the BD)

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
5,148 Views
Registered: ‎09-08-2016

Re: Block design-----Create Inteface Port mode selection

Jump to solution

    Yes, you're right.Actually I want to control one module which interface is AXI Lite using JTAG outside of the block design. So firstly I add an instance of this module in the block design and it work normally. But when I add this slave module out side of the block design, the IDL will not work. Finally I found that the AXI slave module's interface is AXI Lite, but the AXI interconnect's interface is AXI4. when you connect the two module inside of the block design, the system will add an AXI protocol convertor between the two module automatically, But if you connect M00_AXI outside of the block design, the system will not add an AXI protocol convertor automatically. So when I add an AXI protocol convertor manually it will work noramally.

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Adventurer
Adventurer
3,115 Views
Registered: ‎09-08-2016

Re: Block design-----Create Inteface Port mode selection

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    OK,Thanks for your help!

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Moderator
Moderator
3,070 Views
Registered: ‎11-09-2015

Re: Block design-----Create Inteface Port mode selection

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Hi @alex_sun,

 

Thank you for giving more detail about your resolution. It could help other users.

 

If everything is clear for you on this subject, please mark the issue as solved.

 

Thanks,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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