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1,161 Views
Registered: ‎02-09-2017

CDMA : DMA SLV ERR and SG SLV ERR

Hi,

 

I am working on a design (Ultrascale+) utilizing a CDMA engine to transmit data back and forth between an on-board RAM and PCIe endpoint AXI BARS. 

 

At the moment  I am getting "DMA SLAVE ERR" (in the case of write transactions) and "SG SLAVE ERR" (in the case of read transactions)  on every single transfer. I have checked and double checked, my addressing of the SG descriptors definitely points to memory addresses that are visible to the AXI bus (not the virutal addresses of the host system). I checked the transactions using an ILA on the two AXI4M interfaces, and sure enough the addresses and data values are all correct. The transfer begins, but after a very short time rresp is asserted on the AXI4M interfaces, which explains the error state of the engine. I am not sure what the cause of this response is? I have successfully used the RAM and AXI BARS in the past with other AXI4M interfaces, though admittedly with more modest data widths (32 bits).

 

Are their any common causes for such an error condition that I should be checking for?

 

Thanks,

 

Brian

 

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4 Replies
Scholar hbucher
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1,156 Views
Registered: ‎03-22-2016

Re: CDMA : DMA SLV ERR and SG SLV ERR

brian.vongunten@speedgoat.ch 

This should be simple to catch. The DMA Slave error is set when any error response is received from the AXI slave. 

So all you need to do is to set an ILA on the AXI bus and watch for error conditions on the BRESP channel.

The AMBA specification lists some causes for this condition:

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slave_error.png
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1,089 Views
Registered: ‎02-09-2017

Re: CDMA : DMA SLV ERR and SG SLV ERR

Thanks @hbucher. I had, in fact, seen the specification you mention, after capturing the bresp/rresp events that are causing the error. I suspect that the errors are originating from the PCIe endpoint (Could also be the DDR4 MIG). The endpoint bridge specifies that the following abnormal conditions will cause the return of a slverr state:

 

Read Illegal burst typeSIB interrupt is asserted.
SLVERR response given with arbitrary read data.
Write Illegal burst typeSIB interrupt is asserted.
Write data is discarded.
SLVERR response given.
   
   
Read Completion timeoutSCT interrupt is asserted.
SLVERR response given with arbitrary read data.
Read Poison bit in completionCompletion data is discarded.
SEP interrupt is asserted.
SLVERR response given with arbitrary read data.
Read Completer Abort (CA) status
returned
SCA interrupt is asserted.
SLVERR response given with arbitrary read data.

 

Honestly not sure now how to determine what exactly is the root cause of one (or more) of these conditions.

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1,125 Views
Registered: ‎02-09-2017

Re: CDMA : DMA SLV ERR and SG SLV ERR

Thanks @hbucher, I had actually seen the part of the specification you mentioned. I am pretty sure the error is originating with the PCIe endpoint, since I am getting an SG SLV ERR, in the case of reads, and that AXI4M Scatter gather connection does not write to my DDR4 RAM. According to the data sheet for the PCIe bridged endpoint, the error conditions which can cause a return of a SLV ERR from the slave interface are:

 

- Illegal Burst Type (read or write)

- completion timeout (read)

-poison bit in completion (read)

-completer abort (read)

 

I am strongly supposing that the cause of the problem is a read issue with the AXI4M Slave connection of the PCIe endpoint. However, I can't really grok what I can do about that? I have no influence on the burst type. I assume that the CDMA endpoint only issues INCR (incrementing burst) transactions, so that rules out the first case. It could be one of the other error causes, but the endpoint is used for other purposes, including DMA operations with the streaming engine, (successfully) so I am at a bit of a loss.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: CDMA : DMA SLV ERR and SG SLV ERR

brian.vongunten@speedgoat.ch If you place a ILA on the slave port of the PCIe you should be able to easily catch this error.

 

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