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Participant ssankar1
Participant
3,956 Views
Registered: ‎05-14-2015

Cameral link reciver using Select io Wizard

Hi,

 

I am trying to make  a camera link reciver  to get data from a high speed camera using Zynq FPGA The select io wizard in Vivado has a camera link operation . However it doesnt seem to be doing the right thing according to my understanding;. It takes in the differential clock from the camera link . and further divides it by 7 and sends it as the output clock. for the parallel data.

 

The o/p clock for the parallel data should be of same as freqquency the incoming pixel clock. There was a similar issue discussed in an older forum  for the Camera link transmitter ip.

 

http://forums.xilinx.com/t5/General-Technical-Discussion/Camera-link-transmitter-using-SelectIO-IP/td-p/418087

 

They had concluded that it is a bug in the IP. 

 

Can anyone guide me on this.  Should we do the design on our own , or is there some work around .

 

Also in the camera link reciver IP there is no DDR option. It  greys out and the default is SDR.

 

 

 

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1 Reply
Scholar trenz-al
Scholar
3,942 Views
Registered: ‎11-09-2013

Re: Cameral link reciver using Select io Wizard

cameralink should use SDR this is correct.

 

we are also doing CL ip core, but no ETA on release date yet

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