09-21-2018 03:10 PM
We are designing a board with a "shared multi-master" SPI bus that connects a Microcontroller SPI peripheral to the Zynq QSPI and Zynq SPI interfaces. The Zynq PS will boot from NOR Flash on the QSPI interface, then access another NOR Flash on its SPI interface to read the PL bitstreams required to configure the PL logic. The Micro must have access to the same shared multi-master SPI bus in order to perform updates of the images of both NOR Flash devices using "direct programming".
To avoid SPI bus contention, the Zynq SPI interface and Zynq QSPI interfaces must both be disconnected from the shared SPI when the Micro needs to act as master. The Zynq SPI controller supports a "multi-master" bus mode that allows it to be disabled by PS software to 3-state the I/O to avoid bus contention. But I have found no similar capability for temporarily disconnecting the Zync QSPI controller from its MIO interface pins. If both GQSPI and LQSPI controllers are disabled using their respective enable bits found in the xQSPI_En registers, will their MIO pins revert to high impedance? Is it possible for the PS software to disable the QSPI peripheral, then reconfigure the MIO to disconnect the QSPI controller pins, after the PS has booted? Will this impact the next POR reboot? (I would assume the Zynq BootROM code must reconfigure the QSPI interface anyway on the next POR reboot if the QSPI32 boot mode is selected by the PS_Mode pins to boot from the QSPI Nor Flash.)
Thanks for any input.
09-24-2018 02:28 AM
You can configure the MIOs once you boot and they will not impact on Nextboot. If you configure them in FSBL then FSBL will configure it for every boot.
Did you try disabling the controllers config.leg_flsh=0 & Lqspi.SPI_EN=0?
Don't forget to reply, kudo, and accept as solution.
09-25-2018 11:07 AM
Thanks very much for the reply Kranthi.
To make sure I understand, the MIOs can be reconfigured after the Zynq PS has booted to disable the QSPI boot interface, by using the config.leg_flsh bit and LQSPI_EN.SPI_EN bit. This can be done within the FSBL (since the FSBL has already been copied from QSPI Flash into OCM by this point in the boot process) so that the same QSPI reconfiguration occurs after every boot. This change will not impact the ability to reboot after a POR since the BootROM code that boots the PS from the boot image in the QSPI NOR Flash still configures the QSPI interface as needed for the boot process (prior to FSBL execution)? Does this all sound correct? If so, this scheme sounds like exactly what we need. Is it only the 2 bits mentioned that would need changed in the configuration registers? I guess this means that the BootROM code always uses the LQSPI controller mode (not GQSPI) for the boot from QSPI flash?
We have not tried disabling the controllers using the bits you mentioned since we do not yet have hardware. We are still working on our custom board schematic. We need to understand this shared SPI bus design in order to incorporate into our design. Will all the Zynq QSPI MIO signals go to high-impedance if the controllers are disabled by resetting the 2 bits you suggest?