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Scholar helmutforren
Scholar
527 Views
Registered: ‎06-23-2014

Can't find AXI SPI for adding to block diagram

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I'm using Vivado 2018.1 and the Kintex 7, both 160T and 325T in ffg676 package.

 

Another forum post ( https://forums.xilinx.com/t5/Networking-and-Connectivity/AXI-Quad-SPI-AXI-SPI/td-p/770510 ) mentions bot the AXI SPI and the AXI Quad SPI.  From a block diagram, when I click on the "+" at the top in order to add a module, I can find the AXI Quad SPI, but I can't find the AXI SPI.  My need is only single, standard SPI.  Looking at resource usage, the AXI Quad SPI appears to require dramatically more than the AXI SPI.  For this reason I'd rather use the AXI SPI that I can't find.

 

[EDIT: Oh yes, and I'll need a MicroBlaze bare metal driver to talk to it, if that makes a difference in which IP that I use.]

 

Is the AXI SPI deprecated?  Is there an easy way to get it into the block diagram?  (I need the easy way, as my project has far too many other time consuming tasks not yet completed, LOL.)

 

Thanks,

Helmut

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Moderator
Moderator
490 Views
Registered: ‎07-31-2012

Re: Can't find AXI SPI for adding to block diagram

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Hi @helmutforren,

 

AXI QSPI can be configured as standard x8 as shown below and explained in https://forums.xilinx.com/t5/Networking-and-Connectivity/AXI-Quad-SPI-AXI-SPI/td-p/770510 .

In 7series there is not AXI SPI IP as such all you need is to configure as shown in screenshot.

 

Regards

Praveen


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AXI_QSPI_standardmode.png
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Moderator
Moderator
491 Views
Registered: ‎07-31-2012

Re: Can't find AXI SPI for adding to block diagram

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Hi @helmutforren,

 

AXI QSPI can be configured as standard x8 as shown below and explained in https://forums.xilinx.com/t5/Networking-and-Connectivity/AXI-Quad-SPI-AXI-SPI/td-p/770510 .

In 7series there is not AXI SPI IP as such all you need is to configure as shown in screenshot.

 

Regards

Praveen


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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
AXI_QSPI_standardmode.png
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Scholar helmutforren
Scholar
466 Views
Registered: ‎06-23-2014

Re: Can't find AXI SPI for adding to block diagram

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If I can continue asking...

 

This darned part has too many unused connections!  I'm using these sparse few.  Does this sound correct, for this guy being master?  I'm bringing them to external pins.

 

MOSI = io0_o = Master out, Slave in (input)

MISO = io1_1 = Master in, Slave out (output)

SS = ss_o[0:0] = Slave Select (output)

SCLK = cfgmclk = SPI Clock (output)

 

Left unused are the other flavors of io0*, io1*, and STARTUP_IO:*

 

[EDIT:  Further found I must drive ext_spi_clk.  Page 22 of pg153 April 4, 2018 says it must be slower than AXI clock.  Was driving AXI clock from Clocking Wizard that produced 200MHz sysclk and 100MHz microblaze clock that goes to AXI.  Added third output at 50MHz.  Configured AXI quad SPI to divide by 2.  Expecting 25MHz on SCLK above to drive chip with 26MHz max.]

 

[EDIT: I'm getting closer.  SCLK should be driven by sck_o.  Unfortunately, the IP defaulted to STARTUP enabled, which removed sck_o from availability.  I don't need STARTUP.  I turned it off and sck_o became available.  Also, the doc says sck_i is only available in slave mode.  I have the IP configured for master mode, yet sck_i is still there.  The slave mode comment isn't made for all the other _i, but it seems like it should be.  Yet those are still there too.  Lot's of signals present that shouldn't be connected...]

 

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